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authorMarshall Dawson <marshalldawson3rd@gmail.com>2019-06-20 08:47:58 -0600
committerMartin Roth <martinroth@google.com>2019-08-09 20:46:41 +0000
commite2c24f783d78c582fb56625768b9ac424b5943c9 (patch)
treec04ace65174be7ede94de015e7115aa7053fdb5d /src/soc/amd/picasso/include
parent34c30565b0ef3b1ff79943768ecc2f4012bf6b86 (diff)
soc/amd/picasso: Update i2c support
Change the stoneyridge definitions into picasso. The named 0 and 1 buses are controlled by the PSP and not directly accessible by host firmware. I2C4 operates only in slave mode so is not added to to the bus clear-after-reset sequence. The I2C controller is fundamentally the same as on Stoney Ridge so the ability to clear a potentially jammed bus is still required. Program Picasso's new pad control registers in the MISC AcpiMmio space according to the recommended settings. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ibbc5504ebc36654e28c79fe3ae17cc0d9255118f Reviewed-on: https://review.coreboot.org/c/coreboot/+/33763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/picasso/include')
-rw-r--r--src/soc/amd/picasso/include/soc/i2c.h18
-rw-r--r--src/soc/amd/picasso/include/soc/iomap.h11
-rw-r--r--src/soc/amd/picasso/include/soc/southbridge.h42
3 files changed, 49 insertions, 22 deletions
diff --git a/src/soc/amd/picasso/include/soc/i2c.h b/src/soc/amd/picasso/include/soc/i2c.h
index fb9b113c8e..d129fc1f1f 100644
--- a/src/soc/amd/picasso/include/soc/i2c.h
+++ b/src/soc/amd/picasso/include/soc/i2c.h
@@ -23,24 +23,18 @@ struct soc_amd_i2c_save {
uint8_t mux_value;
};
-#define GPIO_I2C0_SCL BIT(0)
-#define GPIO_I2C1_SCL BIT(1)
-#define GPIO_I2C2_SCL BIT(2)
-#define GPIO_I2C3_SCL BIT(3)
-#define GPIO_I2C_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
-
-#define I2C0_SCL_PIN GPIO_145
-#define I2C1_SCL_PIN GPIO_147
+#define GPIO_I2C2_SCL BIT(2)
+#define GPIO_I2C3_SCL BIT(3)
+#define GPIO_I2C_MASK (BIT(2) | BIT(3))
+
#define I2C2_SCL_PIN GPIO_113
#define I2C3_SCL_PIN GPIO_19
-#define GPIO_I2C0_ADDRESS GPIO_BANK2_CONTROL(I2C0_SCL_PIN)
-#define GPIO_I2C1_ADDRESS GPIO_BANK2_CONTROL(I2C1_SCL_PIN)
#define GPIO_I2C2_ADDRESS GPIO_BANK1_CONTROL(I2C2_SCL_PIN)
#define GPIO_I2C3_ADDRESS GPIO_BANK0_CONTROL(I2C3_SCL_PIN)
+#define GPIO_SCL_HIGH 0
+#define GPIO_SCL_LOW GPIO_OUTPUT_ENABLE
-#define I2C0_SCL_PIN_IOMUX_GPIOxx GPIO_145_IOMUX_GPIOxx
-#define I2C1_SCL_PIN_IOMUX_GPIOxx GPIO_147_IOMUX_GPIOxx
#define I2C2_SCL_PIN_IOMUX_GPIOxx GPIO_113_IOMUX_GPIOxx
#define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx
diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h
index 4e11cbd4c8..ad0e7c4609 100644
--- a/src/soc/amd/picasso/include/soc/iomap.h
+++ b/src/soc/amd/picasso/include/soc/iomap.h
@@ -44,9 +44,16 @@
#define ALINK_AHB_ADDRESS 0xfedc0000
/* I2C fixed address */
-#define I2C_BASE_ADDRESS 0xfedc2000
+#define APU_I2C2_BASE 0xfedc4000
+#define APU_I2C3_BASE 0xfedc5000
+#define APU_I2C4_BASE 0xfedc6000
+#define APU_I2C_MIN_BUS 2
+#define APU_I2C_MAX_BUS 4
+#define APU_I2C_BLOCK_SIZE 0x1000
+#define I2C_BASE_ADDRESS APU_I2C2_BASE
#define I2C_DEVICE_SIZE 0x00001000
-#define I2C_DEVICE_COUNT 4
+#define I2C_DEVICE_COUNT 3
+
#if CONFIG(HPET_ADDRESS_OVERRIDE)
#error HPET address override is not allowed and must be fixed at 0xfed00000
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index 8c96aa7f99..803c638164 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -178,13 +178,38 @@
#define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */
#define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */
#define OSCOUT2_CLK_OUTPUT_ENB BIT(7) /* 0 = Enabled, 1 = Disabled */
+#define MISC_I2C0_PAD_CTRL 0xd8
+#define MISC_I2C1_PAD_CTRL 0xdc
+#define MISC_I2C2_PAD_CTRL 0xe0
+#define MISC_I2C3_PAD_CTRL 0xe4
+#define I2C_PAD_CTRL_NG_MASK (BIT(0) + BIT(1) + BIT(2) + BIT(3))
+#define I2C_PAD_CTRL_NG_NORMAL 0xc
+#define I2C_PAD_CTRL_RX_SEL_MASK (BIT(4) + BIT(5))
+#define I2C_PAD_CTRL_RX_SHIFT 4
+#define I2C_PAD_CTRL_RX_SEL_OFF (0 << I2C_PAD_CTRL_RX_SHIFT)
+#define I2C_PAD_CTRL_RX_SEL_3_3V (1 << I2C_PAD_CTRL_RX_SHIFT)
+#define I2C_PAD_CTRL_RX_SEL_1_8V (3 << I2C_PAD_CTRL_RX_SHIFT)
+#define I2C_PAD_CTRL_PULLDOWN_EN BIT(6)
+#define I2C_PAD_CTRL_FALLSLEW_MASK (BIT(7) + BIT(8))
+#define I2C_PAD_CTRL_FALLSLEW_SHIFT 7
+#define I2C_PAD_CTRL_FALLSLEW_STD (0 << I2C_PAD_CTRL_FALLSLEW_SHIFT)
+#define I2C_PAD_CTRL_FALLSLEW_LOW (1 << I2C_PAD_CTRL_FALLSLEW_SHIFT)
+#define I2C_PAD_CTRL_FALLSLEW_EN BIT(9)
+#define I2C_PAD_CTRL_SPIKE_RC_EN BIT(10)
+#define I2C_PAD_CTRL_SPIKE_RC_SEL BIT(11) /* 0 = 50ns, 1 = 20ns */
+#define I2C_PAD_CTRL_CAP_DOWN BIT(12)
+#define I2C_PAD_CTRL_CAP_UP BIT(13)
+#define I2C_PAD_CTRL_RES_DOWN BIT(14)
+#define I2C_PAD_CTRL_RES_UP BIT(15)
+#define I2C_PAD_CTRL_BIOS_CRT_EN BIT(16)
+#define I2C_PAD_CTRL_SPARE0 BIT(17)
+#define I2C_PAD_CTRL_SPARE1 BIT(18)
/* FCH AOAC Registers 0xfed81e00 */
#define FCH_AOAC_D3_CONTROL_CLK_GEN 0x40
-#define FCH_AOAC_D3_CONTROL_I2C0 0x4a
-#define FCH_AOAC_D3_CONTROL_I2C1 0x4c
#define FCH_AOAC_D3_CONTROL_I2C2 0x4e
#define FCH_AOAC_D3_CONTROL_I2C3 0x50
+#define FCH_AOAC_D3_CONTROL_I2C4 0x52
#define FCH_AOAC_D3_CONTROL_UART0 0x56
#define FCH_AOAC_D3_CONTROL_UART1 0x58
#define FCH_AOAC_D3_CONTROL_AMBA 0x62
@@ -198,10 +223,9 @@
#define FCH_AOAC_IS_SW_CONTROL BIT(7)
#define FCH_AOAC_D3_STATE_CLK_GEN 0x41
-#define FCH_AOAC_D3_STATE_I2C0 0x4b
-#define FCH_AOAC_D3_STATE_I2C1 0x4d
#define FCH_AOAC_D3_STATE_I2C2 0x4f
#define FCH_AOAC_D3_STATE_I2C3 0x51
+#define FCH_AOAC_D3_STATE_I2C4 0x53
#define FCH_AOAC_D3_STATE_UART0 0x57
#define FCH_AOAC_D3_STATE_UART1 0x59
#define FCH_AOAC_D3_STATE_AMBA 0x63
@@ -289,12 +313,11 @@ struct picasso_aoac {
};
typedef struct aoac_devs {
- unsigned int :5;
- unsigned int ic0e:1; /* 5: I2C0 */
- unsigned int ic1e:1; /* 6: I2C1 */
+ unsigned int :7;
unsigned int ic2e:1; /* 7: I2C2 */
unsigned int ic3e:1; /* 8: I2C3 */
- unsigned int :2;
+ unsigned int ic4e:1; /* 9: I2C4 */
+ unsigned int :1;
unsigned int ut0e:1; /* 11: UART0 */
unsigned int ut1e:1; /* 12: UART1 */
unsigned int :2;
@@ -370,4 +393,7 @@ void i2c_soc_early_init(void);
/* Initialize all the i2c buses that are not marked with early init. */
void i2c_soc_init(void);
+/* Allow the board to change the default I2C pad configuration */
+void mainboard_i2c_override(int bus, uint32_t *pad_settings);
+
#endif /* __PICASSO_SB_H__ */