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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2020-10-27 16:32:11 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-10-30 13:03:23 +0000 |
| commit | 902518e983d5aa3c1fdb5dfd91ca1fb468117191 (patch) | |
| tree | d989485c7b9187cfa4e664b785b20b4d39945e5e /src/soc/amd/picasso/include | |
| parent | c5e28abaf803465ae4bfec1904618497e077ca50 (diff) | |
soc/amd/picasso: Fix the PSP SMI trigger info
Align coreboot's PSP MboxBiosCmdSmmInfo setup to how AGESA's PSP
library was implemented. The trigger address must be an SMI trigger
register. Assign one of the reserved triggers to the PSP.
The #define of SMITYPE_PSP 33 is still correct and is intentionally
unmodified.
This patch should be innocuous as the system doesn't currently support
SMI-based features of the PSP. The call only exists so the PSP will
honor a mailbox command during S3 suspend.
BUG=b:171815390
TEST=Run SST on Morphius
BRANCH=Zork
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I74029271a522a4f23e54fd76f99a8e3eb0dd4d55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46854
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso/include')
| -rw-r--r-- | src/soc/amd/picasso/include/soc/smi.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index a629fc5541..0529ef6877 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -160,6 +160,7 @@ #define SMI_TIMER_EN (1 << 15) #define SMI_REG_SMITRIG0 0x98 +# define SMITRIG0_PSP (1 << 25) # define SMITRG0_EOS (1 << 28) # define SMI_TIMER_SEL (1 << 29) # define SMITRG0_SMIENB (1 << 31) |