diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2020-11-30 17:56:59 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-12-02 21:26:50 +0000 |
| commit | 5b3831c75abe5fc50739984eaa70fbada2575bb7 (patch) | |
| tree | 2161a533d7ed50dd612429812f1d6a747cd9c9cd /src/soc/amd/picasso/include | |
| parent | f7b410d4098009e65567f9ad5b7762923830f444 (diff) | |
soc/amd: factor out common AOAC definitions
The register locations and bit definitions are the same for Stoneyridge
and Picasso. Since not all devices are present on all SoCs, keep those
numbers in the SoC-specific code.
Change-Id: Ib882927e399031c376738e5a35793b3d7654b9cf
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/picasso/include')
| -rw-r--r-- | src/soc/amd/picasso/include/soc/southbridge.h | 28 |
1 files changed, 1 insertions, 27 deletions
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index d193661985..8a2ae49b3f 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -183,10 +183,7 @@ #define I2C_PAD_CTRL_SPARE0 BIT(17) #define I2C_PAD_CTRL_SPARE1 BIT(18) -/* FCH AOAC Registers 0xfed81e00 */ -#define AOAC_DEV_D3_CTL(device) (0x40 + device * 2) -#define AOAC_DEV_D3_STATE(device) (AOAC_DEV_D3_CTL(device) + 1) - +/* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */ #define FCH_AOAC_DEV_CLK_GEN 0 #define FCH_AOAC_DEV_I2C2 7 #define FCH_AOAC_DEV_I2C3 8 @@ -198,29 +195,6 @@ #define FCH_AOAC_DEV_UART3 26 #define FCH_AOAC_DEV_ESPI 27 -/* Bit definitions for Device D3 Control AOACx0000[40...7E] step 2 */ -#define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1)) -#define FCH_AOAC_D0_UNINITIALIZED 0 -#define FCH_AOAC_D0_INITIALIZED 1 -#define FCH_AOAC_D1_2_3_WARM 2 -#define FCH_AOAC_D3_COLD 3 -#define FCH_AOAC_DEVICE_STATE BIT(2) -#define FCH_AOAC_PWR_ON_DEV BIT(3) -#define FCH_AOAC_SW_PWR_ON_RSTB BIT(4) -#define FCH_AOAC_SW_REF_CLK_OK BIT(5) -#define FCH_AOAC_SW_RST_B BIT(6) -#define FCH_AOAC_IS_SW_CONTROL BIT(7) - -/* Bit definitions for Device D3 State AOACx0000[41...7f] step 2 */ -#define FCH_AOAC_PWR_RST_STATE BIT(0) -#define FCH_AOAC_RST_CLK_OK_STATE BIT(1) -#define FCH_AOAC_RST_B_STATE BIT(2) -#define FCH_AOAC_DEV_OFF_GATING_STATE BIT(3) -#define FCH_AOAC_D3COLD BIT(4) -#define FCH_AOAC_CLK_OK_STATE BIT(5) -#define FCH_AOAC_STAT0 BIT(6) -#define FCH_AOAC_STAT1 BIT(7) - #define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ #define FCH_LEGACY_UART_MAP_SHIFT 8 #define FCH_LEGACY_UART_MAP_SIZE 2 |