soc/amd/picasso: Delete northbridge

Family 17h devices are designed with a new internal architecture,
frequently referred to as the data fabric.  Although designed to
behave somewhat like the older integrated northbridge designs,
the D18Fx definitions are completely new.

The previous northbridge.c was copied from stoneyridge which is
completely different.

Change-Id: Id70cbda99657249179fb8cf5e461dd6a37ec9153
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41265
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 0 insertions, 115 deletions

diff --git a/src/soc/amd/picasso/include/soc/northbridge.h b/src/soc/amd/picasso/include/soc/northbridge.h
deleted file mode 100644
index da33b7e043..0000000000
--- a/src/soc/amd/picasso/include/soc/northbridge.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __PI_PICASSO_NORTHBRIDGE_H__
-#define __PI_PICASSO_NORTHBRIDGE_H__
-
-#include <device/device.h>
-#include <types.h>
-
-/* D1F1 - HDA Configuration Registers */
-#define HDA_DEV_CTRL_STATUS	0x60
-#define   HDA_NO_SNOOP_EN	BIT(11)
-
-/* D18F0 - HT Configuration Registers */
-#define D18F0_NODE_ID		0x60
-#define D18F0_CPU_CNT		0x62 /* BKDG defines as a field in DWORD 0x60 */
-# define CPU_CNT_MASK		0x1f /*  CpuCnt + 1 = no. CPUs */
-#define HT_INIT_CONTROL		0x6c
-# define HTIC_BIOSR_DETECT	((1 << 5) | (1 << 9) | (1 << 10))
-# define HTIC_COLD_RST_DET	BIT(4)
-
-/* D18F1 - Address Map Registers */
-
-/* MMIO base and limit */
-#define D18F1_MMIO_BASE0_LO	0x80
-# define MMIO_WE		(1 << 1)
-# define MMIO_RE		(1 << 0)
-#define D18F1_MMIO_LIMIT0_LO	0x84
-# define MMIO_NP		(1 << 7)
-#define D18F1_IO_BASE0_LO	0xc0
-#define D18F1_IO_BASE1_LO	0xc8
-#define D18F1_IO_BASE2_LO	0xd0
-#define D18F1_IO_BASE3_LO	0xd8
-#define D18F1_MMIO_BASE7_LO	0xb8
-#define D18F1_MMIO_BASELIM0_HI	0x180
-#define D18F1_MMIO_BASE8_LO	0x1a0
-#define D18F1_MMIO_LIMIT8_LO	0x1a4
-#define D18F1_MMIO_BASE11_LO	0x1b8
-#define D18F1_MMIO_BASELIM8_HI	0x1c0
-#define NB_MMIO_BASE_LO(reg)	((reg) * 2 * sizeof(uint32_t) + (((reg) < 8) \
-					? D18F1_MMIO_BASE0_LO \
-					: D18F1_MMIO_BASE8_LO \
-						- 8 * sizeof(uint64_t)))
-#define NB_MMIO_LIMIT_LO(reg)	(NB_MMIO_BASE_LO(reg) + sizeof(uint32_t))
-#define NB_MMIO_BASELIM_HI(reg)	((reg) * sizeof(uint32_t) + (((reg) < 8) \
-					? D18F1_MMIO_BASELIM0_HI \
-					: D18F1_MMIO_BASELIM8_HI \
-						- 8 * sizeof(uint32_t)))
-/* I/O base and limit */
-#define D18F1_IO_BASE0		0xc0
-# define IO_WE			(1 << 1)
-# define IO_RE			(1 << 0)
-#define D18F1_IO_LIMIT0		0xc4
-#define NB_IO_BASE(reg)		((reg) * 2 * sizeof(uint32_t) + D18F1_IO_BASE0)
-#define NB_IO_LIMIT(reg)	(NB_IO_BASE(reg) + sizeof(uint32_t))
-
-#define D18F1_DRAM_HOLE		0xf0
-# define DRAM_HOIST_VALID	(1 << 1)
-# define DRAM_HOLE_VALID	(1 << 0)
-#define D18F1_VGAEN		0xf4
-# define VGA_ADDR_ENABLE	(1 << 0)
-
-/* Bus A D0F5 - Audio Processor */
-#define ACP_I2S_PIN_CONFIG	0x1400	/* HDA, Soundwire, I2S */
-
-void amd_initcpuio(void);
-
-void domain_enable_resources(struct device *dev);
-void domain_set_resources(struct device *dev);
-void fam15_finalize(void *chip_info);
-void set_warm_reset_flag(void);
-int is_warm_reset(void);
-
-#endif /* __PI_PICASSO_NORTHBRIDGE_H__ */
diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h
index cfcc5503a2..a97391e86a 100644
--- a/src/soc/amd/picasso/include/soc/pci_devs.h
+++ b/src/soc/amd/picasso/include/soc/pci_devs.h
@@ -89,48 +89,6 @@
 #define HDA1_DEVFN		PCI_DEVFN(HDA1_DEV, HDA1_FUNC)
 #define SOC_HDA1_DEV		_SOC_DEV(HDA1_DEV, HDA1_FUNC)
 
-/* HT Configuration */
-#define HT_DEV			0x18
-#define HT_FUNC			0
-#define HT_DEVID		0x15b0
-#define HT_DEVFN		PCI_DEVFN(HT_DEV, HT_FUNC)
-#define SOC_HT_DEV		_SOC_DEV(HT_DEV, HT_FUNC)
-
-/* Address Maps */
-#define ADDR_DEV		0x18
-#define ADDR_FUNC		1
-#define ADDR_DEVID		0x15b1
-#define ADDR_DEVFN		PCI_DEVFN(ADDR_DEV, ADDR_FUNC)
-#define SOC_ADDR_DEV		_SOC_DEV(ADDR_DEV, ADDR_FUNC)
-
-/* DRAM Configuration */
-#define DCT_DEV			0x18
-#define DCT_FUNC		2
-#define DCT_DEVID		0x15b2
-#define DCT_DEVFN		PCI_DEVFN(DCT_DEV, DCT_FUNC)
-#define SOC_DCT_DEV		_SOC_DEV(DCT_DEV, DCT_FUNC)
-
-/* Misc. Configuration */
-#define MISC_DEV		0x18
-#define MISC_FUNC		3
-#define MISC_DEVID		0x15b3
-#define MISC_DEVFN		PCI_DEVFN(MISC_DEV, MISC_FUNC)
-#define SOC_MISC_DEV		_SOC_DEV(MISC_DEV, MISC_FUNC)
-
-/* PM Configuration */
-#define PM_DEV			0x18
-#define PM_FUNC			4
-#define PM_DEVID		0x15b4
-#define PM_DEVFN		PCI_DEVFN(PM_DEV, PM_FUNC)
-#define SOC_PM_DEV		_SOC_DEV(PM_DEV, PM_FUNC)
-
-/* Northbridge Configuration */
-#define NB_DEV			0x18
-#define NB_FUNC			5
-#define NB_DEVID		0x15b5
-#define NB_DEVFN		PCI_DEVFN(NB_DEV, NB_FUNC)
-#define SOC_NB_DEV		_SOC_DEV(NB_DEV, NB_FUNC)
-
 /* USB 3.1 */
 #define XHCI0_DEV		0x0
 #define XHCI0_FUNC		3