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authorFurquan Shaikh <furquan@google.com>2020-04-28 18:45:20 -0700
committerFurquan Shaikh <furquan@google.com>2020-04-30 20:59:50 +0000
commita0284db08df3e0150202fd1cfc8c2c675c19f4de (patch)
treede6260608c26aac731c4519f874b7da1b6ea63d7 /src/soc/amd/picasso/include
parent73716d0e924080ea32274a265a8de04e009c3676 (diff)
soc/amd/picasso: Introduce enums for SPI read mode and speed
This change adds enums for spi_read_mode and spi100_speed in preparation for adding these to chip.h in follow-up CLs. This makes it easier to reference what the mainboard is expected to set for these SPI configs. BUG=b:147758054,b:153675510 BRANCH=trembyle-bringup TEST=Verified that SPI configuration is correct for trembyle. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I7f9778b41bd059a50f20993415ebd8702a1ad58e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40823 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso/include')
-rw-r--r--src/soc/amd/picasso/include/soc/southbridge.h54
1 files changed, 36 insertions, 18 deletions
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index cf1d124744..1ce7019526 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -243,15 +243,25 @@
#define SPI_CNTRL0 0x00
#define SPI_BUSY BIT(31)
+enum spi_read_mode {
+ SPI_READ_MODE_NORMAL33M = 0,
+ /* 1 is reserved. */
+ SPI_READ_MODE_DUAL112 = 2,
+ SPI_READ_MODE_QUAD114 = 3,
+ SPI_READ_MODE_DUAL122 = 4,
+ SPI_READ_MODE_QUAD144 = 5,
+ SPI_READ_MODE_NORMAL66M = 6,
+ SPI_READ_MODE_FAST_READ = 7,
+};
+/*
+ * SPI read mode is split into bits 18, 29, 30 such that [30:29:18] correspond to bits [2:0] for
+ * SpiReadMode.
+ */
#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18))
-/* Nominal is 16.7MHz on older devices, 33MHz on newer */
-#define SPI_READ_MODE_NOM 0x00000000
-#define SPI_READ_MODE_DUAL112 ( BIT(29) )
-#define SPI_READ_MODE_QUAD114 ( BIT(29) | BIT(18))
-#define SPI_READ_MODE_DUAL122 (BIT(30) )
-#define SPI_READ_MODE_QUAD144 (BIT(30) | BIT(18))
-#define SPI_READ_MODE_NORMAL66 (BIT(30) | BIT(29) )
-#define SPI_READ_MODE_FAST (BIT(30) | BIT(29) | BIT(18))
+#define SPI_READ_MODE_UPPER_BITS(x) ((((x) >> 1) & 0x3) << 29)
+#define SPI_READ_MODE_LOWER_BITS(x) (((x) & 0x1) << 18)
+#define SPI_READ_MODE(x) (SPI_READ_MODE_UPPER_BITS(x) | \
+ SPI_READ_MODE_LOWER_BITS(x))
#define SPI_ACCESS_MAC_ROM_EN BIT(22)
#define SPI_FIFO_PTR_CLR BIT(20)
#define SPI_ARB_ENABLE BIT(19)
@@ -264,16 +274,24 @@
/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */
#define SPI100_SPEED_CONFIG 0x22
-#define SPI_SPEED_66M (0x0)
-#define SPI_SPEED_33M ( BIT(0))
-#define SPI_SPEED_22M ( BIT(1) )
-#define SPI_SPEED_16M ( BIT(1) | BIT(0))
-#define SPI_SPEED_100M (BIT(2) )
-#define SPI_SPEED_800K (BIT(2) | BIT(0))
-#define SPI_NORM_SPEED_NEW_SH 12
-#define SPI_FAST_SPEED_NEW_SH 8
-#define SPI_ALT_SPEED_NEW_SH 4
-#define SPI_TPM_SPEED_NEW_SH 0
+enum spi100_speed {
+ SPI_SPEED_66M = 0,
+ SPI_SPEED_33M = 1,
+ SPI_SPEED_22M = 2,
+ SPI_SPEED_16M = 3,
+ SPI_SPEED_100M = 4,
+ SPI_SPEED_800K = 5,
+};
+
+#define SPI_SPEED_MASK 0xf
+#define SPI_SPEED_MODE(x, shift) (((x) & SPI_SPEED_MASK) << (shift))
+#define SPI_NORM_SPEED(x) SPI_SPEED_MODE(x, 12)
+#define SPI_FAST_SPEED(x) SPI_SPEED_MODE(x, 8)
+#define SPI_ALT_SPEED(x) SPI_SPEED_MODE(x, 4)
+#define SPI_TPM_SPEED(x) SPI_SPEED_MODE(x, 0)
+
+#define SPI_SPEED_CFG(n, f, a, t) (SPI_NORM_SPEED(n) | SPI_FAST_SPEED(f) | \
+ SPI_ALT_SPEED(a) | SPI_TPM_SPEED(t))
#define SPI100_HOST_PREF_CONFIG 0x2c
#define SPI_RD4DW_EN_HOST BIT(15)