diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2020-12-09 02:18:00 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-12-10 01:22:06 +0000 |
| commit | 5d7fa16c5c7e625371a1fcffedff99027f8b35d8 (patch) | |
| tree | 65eda617570febc8eb63ff408e86f95f5143d626 /src/soc/amd/picasso/include | |
| parent | 1e63e361c68eda9c4876de24416880ab83ec29d9 (diff) | |
soc/amd/picasso/reset: use port and bit defines from cf9_reset.h
The register name and the name of one bit are slightly different, but
have the same functionality.
Change-Id: I025f1c7b2c7643afe245f2275ae6ef45e64b951a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48487
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso/include')
| -rw-r--r-- | src/soc/amd/picasso/include/soc/iomap.h | 1 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/southbridge.h | 5 |
2 files changed, 0 insertions, 6 deletions
diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index cec3aaffc7..43e56582a1 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -83,6 +83,5 @@ #define BIOSRAM_DATA 0xcd5 #define AB_INDX 0xcd8 #define AB_DATA (AB_INDX+4) -#define SYS_RESET 0xcf9 #endif /* AMD_PICASSO_IOMAP_H */ diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 08e242828b..220d92ea7a 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -163,11 +163,6 @@ #define SATA_CAPABILITIES_REG 0xfc #define SATA_CAPABILITY_SPM BIT(12) -/* IO 0xcf9 - Reset control port*/ -#define FULL_RST BIT(3) -#define RST_CMD BIT(2) -#define SYS_RST BIT(1) - /* IO 0xf0 NCP Error */ #define NCP_WARM_BOOT BIT(7) /* Write-once */ |