soc/amd/psp: Add SmmInfo command

Implement the MboxBiosCmdSmmInfo function to inform the PSP of the SoC's
SMM configuration. Once the BootDone command is sent, the PSP only
responds to commands where the buffer is in SMM memory.

Set aside a region for the core-to-PSP command buffer and the
PSP-to-core mailbox. Also add an SMM flag, which the PSP expects to read
as non-zero during an SMI.

Add calls to soc functions for the soc to populate the trigger info and
register info (v2 only).

Add functions to set up the structures needed for the SmmInfo function
in Picasso support. Issue a SW SMI, and add a new handler to call the
new PSP function.

BUG=b:153677737

Change-Id: I10088a53e786db788740e4b388650641339dae75
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

1 files changed, 3 insertions, 0 deletions

diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h
index e890e1319a..fb8061ca16 100644
--- a/src/soc/amd/picasso/include/soc/smi.h
+++ b/src/soc/amd/picasso/include/soc/smi.h
@@ -86,6 +86,7 @@
 #define SMITYPE_NB_GPP_HOT_PLUG		30
 /* 31 Reserved */
 #define SMITYPE_WAKE_L2			32
+#define SMITYPE_PSP			33
 /* 33 - 38 Reserved */
 #define SMITYPE_AZPME			39
 #define SMITYPE_USB_PD_I2C4		40
@@ -186,6 +187,8 @@
 #define SMI_REG_CONTROL8		0xc0
 #define SMI_REG_CONTROL9		0xc4
 
+#define SMI_MODE_MASK			0x03
+
 enum smi_mode {
 	SMI_MODE_DISABLE = 0,
 	SMI_MODE_SMI = 1,