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| author | Furquan Shaikh <furquan@google.com> | 2020-06-05 19:17:00 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-10 18:45:47 +0000 |
| commit | dbce8ba05afa6febbcb5932a03e97e1d4cd982d9 (patch) | |
| tree | 7fe69c8cc392eb733b77ca5f7acf24662da7f500 /src/soc/amd/picasso/include | |
| parent | 46399b5f8d776202239f609278f20b13b026d88e (diff) | |
drivers/intel/fsp2_0: Allow SoC/mainboard to update NvsBufferPtr
This change moves the check for NvsBufferPtr in S3 resume case to
happen just before FSP-M is called. This allows SoC/mainboard code to
set NvsBufferPtr if it doesn't use the default MRC cache driver.
BUG=b:155990176
Change-Id: Ia272573ad7117a0cb851f0bfe6a4c7989bc64cde
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/picasso/include')
0 files changed, 0 insertions, 0 deletions