soc/amd/picasso: remove broken and unused legacy UART support

The UARTs in the Picasso SoC are memory mapped, but there is also some
hardware support that isn't used by any board to make the UARTs behave
like the ones found on legacy x86 machines from the 90s.

In the MMIO mode the MMIO address of the UART controller is passed to
the OS via ACPI. The OS expects the base clock of the UART controller to
be 48MHz (see the cz_uart_desc struct in drivers/acpi/acpi_apd.c and
drivers/tty/serial/8250/8250_dw.c in the Linux kernel) in this case. It
is also possible to enable additional decodes from four 8 byte legacy
I/O locations used for serial ports to the different UART controllers,
which doesn't disable the MMIO access though. The legacy I/O-mapped
serial ports are usually expected to have a base clock of 16*115200Hz
which the hardware can also provide to the UART's baud rate generator.
So there are two possible valid configurations to use the UARTs; either
MMIO access in combination with a 48MHz base clock or the legacy I/O
decode with a ~1.8MHz base clock.

The existing code unconditionally generates ACPI objects for all enabled
UARTs, so those shouldn't be put into legacy mode and switching the base
clock to ~1.8MHz was only done in the case that the UART was used as
coreboot console UART which still used the MMIO access, but the lower
base clock. Since no board even selects this option and it's rather
invasive to properly implement this feature, just drop the corresponding
broken code.

TEST=SoC UART console still works on Mandolin.

Change-Id: I26fa8fdfc781b583ba56ac4dbcbbfb6100e84852
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reported-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49371
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 0 insertions, 16 deletions

diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index 220d92ea7a..c7f30e24ec 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -13,14 +13,6 @@
  *  - fixed addresses offset from 0xfed80000
  */
 
-/* SMBus controller registers:  0xfed80000 or D14F0 */
-#define SMB_UART_CONFIG			0xfc
-#define   SMB_UART3_1_8M		BIT(31) /* defaults are 0 = 48MHz */
-#define   SMB_UART2_1_8M		BIT(30)
-#define   SMB_UART1_1_8M		BIT(29)
-#define   SMB_UART0_1_8M		BIT(28)
-#define   SMB_UART_1_8M_SHIFT		28
-
 /* Power management registers:  0xfed80300 or index/data at IO 0xcd6/cd7 */
 #define PM_PCI_CTRL			0x08
 #define   FORCE_SLPSTATE_RETRY		BIT(25)
@@ -144,13 +136,6 @@
 #define FCH_AOAC_DEV_ESPI		27
 
 #define FCH_LEGACY_UART_DECODE		(ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */
-#define   FCH_LEGACY_UART_MAP_SHIFT	8
-#define   FCH_LEGACY_UART_MAP_SIZE	2
-#define   FCH_LEGACY_UART_MAP_MASK	0x3
-#define   FCH_LEGACY_UART_RANGE_2E8	0
-#define   FCH_LEGACY_UART_RANGE_2F8	1
-#define   FCH_LEGACY_UART_RANGE_3E8	2
-#define   FCH_LEGACY_UART_RANGE_3F8	3
 
 #define PM1_LIMIT			16
 #define GPE0_LIMIT			28
@@ -196,7 +181,6 @@ void southbridge_final(void *chip_info);
 void southbridge_init(void *chip_info);
 void fch_pre_init(void);
 void fch_early_init(void);
-void set_uart_legacy_config(unsigned int uart_idx, unsigned int range_idx);
 
 /* Initialize all the i2c buses that are marked with early init. */
 void i2c_soc_early_init(void);