diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-06-22 16:15:06 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-08-09 20:22:46 +0000 |
| commit | ad1fdac9879eb0aba5d7f05752ae010f3bdcff66 (patch) | |
| tree | 391a14ac81983ea0d65f28712f5e1a10bc533320 /src/soc/amd/picasso/include | |
| parent | d881367c0862a8b94324be2283f4afab8bcb8438 (diff) | |
soc/amd/picasso: Remove IOAPIC2
Remove the Family 15h device. It's not in Family 17h documentation
and isn't detectable with HDT.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ifa9c06f78f39a3ec3b555d4ecc542172cd44a0b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33990
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso/include')
| -rw-r--r-- | src/soc/amd/picasso/include/soc/iomap.h | 3 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/northbridge.h | 26 |
2 files changed, 2 insertions, 27 deletions
diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 2870103e93..4e11cbd4c8 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -18,8 +18,9 @@ #define __SOC_PICASSO_IOMAP_H__ /* MMIO Ranges */ +/* IO_APIC_ADDR defined in arch/x86 0xfec00000 */ #define SPI_BASE_ADDRESS 0xfec10000 -#define IO_APIC2_ADDR 0xfec20000 +#define ESPI_BASE_ADDRESS 0xfec20000 /* * AcpiMmio blocks are at fixed offsets from FED8_0000h and enabled in PMx04[1]. diff --git a/src/soc/amd/picasso/include/soc/northbridge.h b/src/soc/amd/picasso/include/soc/northbridge.h index 57373c9a08..667a49eb0c 100644 --- a/src/soc/amd/picasso/include/soc/northbridge.h +++ b/src/soc/amd/picasso/include/soc/northbridge.h @@ -20,28 +20,6 @@ #include <device/device.h> #include <types.h> -/* D0F0 - Root Complex */ - -/* NB IOAPIC registers */ -#define NB_IOAPIC_INDEX 0xf8 -#define NB_IOAPIC_DATA 0xfc -#define NB_IOAPIC_FEATURE_CTRL 0x00 -#define NB_IOAPIC_ADDRESS_LOW 0x01 -#define NB_IOAPIC_ADDRESS_HIGH 0x02 -#define NB_IOAPIC_GBIF_IRR 0x0f -#define NB_IOAPIC_BR0_IRR 0x10 -#define NB_IOAPIC_BR1_IRR 0x11 -#define NB_IOAPIC_BR2_IRR 0x12 -#define NB_IOAPIC_BR3_IRR 0x13 -#define NB_IOAPIC_BR4_IRR 0x14 -#define NB_IOAPIC_APG_IRR 0x2f -#define NB_IOAPIC_SPG_IRR 0x30 -#define NB_IOAPIC_SER_IRQ_IRR 0x31 -#define NB_IOAPIC_SCRATCH0 0x3e -#define NB_IOAPIC_SCRATCH1 0x3f - -#define AP_SCRATCH_REG NB_IOAPIC_SCRATCH0 - /* D1F1 - HDA Configuration Registers */ #define HDA_DEV_CTRL_STATUS 0x60 #define HDA_NO_SNOOP_EN BIT(11) @@ -104,10 +82,6 @@ void amd_initcpuio(void); void domain_enable_resources(struct device *dev); void domain_set_resources(struct device *dev); void fam15_finalize(void *chip_info); -uint32_t nb_ioapic_read(unsigned int index); -void nb_ioapic_write(unsigned int index, uint32_t value); -void *get_ap_entry_ptr(void); -void set_ap_entry_ptr(void *entry); void set_warm_reset_flag(void); int is_warm_reset(void); |