diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-06-13 16:03:47 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-07-06 18:21:39 +0000 |
| commit | 78025f6c5c8a65d662c3af7d8de2ad5a59752419 (patch) | |
| tree | 7e8a577d9cd4aa0716cfe8976c585491079dcf51 /src/soc/amd/picasso/include | |
| parent | fcfa35670a191d2313324fb313bac237e7a3d0c6 (diff) | |
soc/amd/picasso: Remove all AGESA references
Family 17h will not use the Arch2008 (a.k.a. v5) wrapper. Remove
all source, support functions, and comments related to AGESA.
Family 17h requires v9 which has no similarities to v5 for
integration into a host firmware. AGESA v9 support will be added
via subsequent patches into the appropriate locations.
Change-Id: Iea1a41941a0ba364a6abaaf31cc8e1145db4a236
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/picasso/include')
| -rw-r--r-- | src/soc/amd/picasso/include/soc/cpu.h | 10 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/northbridge.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/southbridge.h | 4 |
3 files changed, 5 insertions, 11 deletions
diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index 7d4764567a..7bc1810dba 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -18,16 +18,8 @@ #include <device/device.h> -/* - * Set a variable MTRR in bootblock and/or romstage. AGESA will use the lowest - * numbered registers. Any values defined below are subtracted from the - * highest numbered registers. - * - * todo: Revisit this once AGESA no longer programs MTRRs. - */ #define SOC_EARLY_VMTRR_FLASH 1 -#define SOC_EARLY_VMTRR_CAR_HEAP 2 -#define SOC_EARLY_VMTRR_TEMPRAM 3 +#define SOC_EARLY_VMTRR_TEMPRAM 2 void picasso_init_cpus(struct device *dev); void check_mca(void); diff --git a/src/soc/amd/picasso/include/soc/northbridge.h b/src/soc/amd/picasso/include/soc/northbridge.h index f7df2772c5..65705b93f3 100644 --- a/src/soc/amd/picasso/include/soc/northbridge.h +++ b/src/soc/amd/picasso/include/soc/northbridge.h @@ -110,6 +110,8 @@ enum { SMM_SUBREGION_NUM, }; +void amd_initcpuio(void); + /* * Fills in the arguments for the entire SMM region covered by chipset * protections. e.g. TSEG. diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index b28522e60f..565ab3084d 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -322,7 +322,7 @@ void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); void bootblock_fch_early_init(void); void bootblock_fch_init(void); /** - * @brief Save the UMA bize returned by AGESA + * @brief Save the UMA bize * * @param size = in bytes * @@ -330,7 +330,7 @@ void bootblock_fch_init(void); */ void save_uma_size(uint32_t size); /** - * @brief Save the UMA base address returned by AGESA + * @brief Save the UMA base address * * @param base = 64bit base address * |