soc/amd/*/i2c: factor out common I2C pad configuration

The I2C pad control registers of Picasso and Cezanne are identical and
the one of Sabrina is a superset of it, so factor out the functionality.
To avoid having devicetree settings that contain raw register bits, the
i2c_pad_control struct is introduced and used. The old Picasso code for
this had the RX level hard-coded for 3.3V I2C interfaces, so keep it
this way in this patch but add a TODO  for future improvements.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

1 files changed, 6 insertions, 15 deletions

diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c
index 40cf556b04..ebc833df2a 100644
--- a/src/soc/amd/picasso/i2c.c
+++ b/src/soc/amd/picasso/i2c.c
@@ -40,22 +40,13 @@ void i2c_set_bar(unsigned int bus, uintptr_t bar)
 
 void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
 {
-	uint32_t pad_ctrl;
+	/* TODO: Picasso supports I2C RX pad configurations 3.3V, 1.8V and off, so make this
+	   configurable. */
+	const struct i2c_pad_control ctrl = {
+		.rx_level = I2C_PAD_RX_3_3V,
+	};
 
-	pad_ctrl = misc_read32(MISC_I2C_PAD_CTRL(bus));
-
-	pad_ctrl &= ~I2C_PAD_CTRL_NG_MASK;
-	pad_ctrl |= I2C_PAD_CTRL_NG_NORMAL;
-
-	pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK;
-	pad_ctrl |= I2C_PAD_CTRL_RX_SEL_3_3V;
-
-	pad_ctrl &= ~I2C_PAD_CTRL_FALLSLEW_MASK;
-	pad_ctrl |= cfg->speed == I2C_SPEED_STANDARD ?
-		I2C_PAD_CTRL_FALLSLEW_STD : I2C_PAD_CTRL_FALLSLEW_LOW;
-	pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN;
-
-	misc_write32(MISC_I2C_PAD_CTRL(bus), pad_ctrl);
+	fch_i2c_pad_init(bus, cfg->speed, &ctrl);
 }
 
 const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs)