diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2020-07-24 19:10:03 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-07-27 18:42:14 +0000 |
| commit | bcb3d0397303272ed201f46bb41c4d029f384fa1 (patch) | |
| tree | 1e722a1e32bf940ab90146f92e47f0e876bd36cd /src/soc/amd/picasso/fsp_params.c | |
| parent | 1e5edb48c3dc66ef73a43413a27baff5a43ef268 (diff) | |
soc/amd/picasso: make USB over-current pin mapping configurable
Neither the family 17h model 10-1Fh PPR nor the internal FSP source
seems to have the mapping of the USB OC pins to the four bit values, so
this is based on the information from the family 15h model 70-7Fh BKDG
which also corresponds to what I'd have expected here.
BUG=b:162010077
Change-Id: I581ef1d730e9d729d9849d7e73ef1c1b67b2c4cf
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/amd/picasso/fsp_params.c')
| -rw-r--r-- | src/soc/amd/picasso/fsp_params.c | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index 8e6703e436..1dbb8e57b5 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -98,17 +98,28 @@ static void fsp_fill_pcie_ddi_descriptors(FSP_S_CONFIG *scfg) static void fsp_usb_oem_customization(FSP_S_CONFIG *scfg, const struct soc_amd_picasso_config *cfg) { + size_t i; + ASSERT(FSPS_UPD_USB2_PORT_COUNT == USB_PORT_COUNT); + /* each OC mapping in xhci_oc_pin_select is 4 bit per USB port */ + ASSERT(2 * sizeof(scfg->xhci_oc_pin_select) >= USB_PORT_COUNT); scfg->xhci0_force_gen1 = cfg->xhci0_force_gen1; if (cfg->has_usb2_phy_tune_params) { - for (size_t i = 0; i < FSPS_UPD_USB2_PORT_COUNT; i++) { + for (i = 0; i < FSPS_UPD_USB2_PORT_COUNT; i++) { memcpy(scfg->fch_usb_2_port_phy_tune[i], &cfg->usb_2_port_tune_params[i], sizeof(scfg->fch_usb_2_port_phy_tune[0])); } } + + /* lowest nibble of xhci_oc_pin_select corresponds to OC mapping of first USB port */ + for (i = 0; i < USB_PORT_COUNT; i++) { + scfg->xhci_oc_pin_select &= ~(0xf << (i * 4)); + scfg->xhci_oc_pin_select |= + (cfg->usb_port_overcurrent_pin[i] & 0xf) << (i * 4); + } } void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |