diff options
| author | Varshit Pandya <pandyavarshit@gmail.com> | 2024-02-09 18:26:32 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-12 13:58:32 +0000 |
| commit | ef513773abbfd4892f2017f14db818e9b973f8be (patch) | |
| tree | 7049f15ca8d6982f59792c20795b354c986d6334 /src/soc/amd/picasso/fch.c | |
| parent | ddd002010fe4fe693e7345b490f65ea4bfca0896 (diff) | |
soc/amd/picasso: Use pcie_gpp_dxio_update_clk_req_config
This function turns off gpp_clk for the devices which are disabled, and
adds the code to fix up the clock configuration depending on dxio
descriptors. Also this brings picasso in line with cezanne, mendocino
and phoenix. This also prepares picasso to use the common function
gpp_clk_setup_common.
Change-Id: Ice2e3a5a78359da9a438434c7d4aa1eca878d396
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80413
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/picasso/fch.c')
| -rw-r--r-- | src/soc/amd/picasso/fch.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index bfe65a2b9e..efa008d6bb 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -7,6 +7,7 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <amdblocks/amd_pci_util.h> +#include <amdblocks/pci_clk_req.h> #include <amdblocks/reset.h> #include <amdblocks/acpimmio.h> #include <amdblocks/acpi.h> @@ -174,7 +175,7 @@ static void al2ahb_clock_gate(void) /* configure the general purpose PCIe clock outputs according to the devicetree settings */ static void gpp_clk_setup(void) { - const struct soc_amd_picasso_config *cfg = config_of_soc(); + struct soc_amd_picasso_config *cfg = config_of_soc(); /* look-up table to be able to iterate over the PCIe clock output settings */ const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = { @@ -189,6 +190,8 @@ static void gpp_clk_setup(void) uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL); + pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0], + ARRAY_SIZE(cfg->gpp_clk_config)); for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) { gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]); /* |