soc/amd/picasso: Remove all PSP runtime functions

Remove the mailbox call to notify the PSP that DRAM is ready.  This
is not supported on Family 17h.

Remove the selectable SMU firmware.  This is a feature of the PSP
bootloader and the standard bootloader doesn't contain the ability.

Clean up additional mentions of PSP within picasso.

Change-Id: I8abeb4c375dbff3b438cd18ccaaf66e11c86e72e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>

1 files changed, 0 insertions, 17 deletions

diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c
index fc9e9ecf06..bee2b4b49f 100644
--- a/src/soc/amd/picasso/cpu.c
+++ b/src/soc/amd/picasso/cpu.c
@@ -121,23 +121,6 @@ static void model_15_init(struct device *dev)
 {
 	check_mca();
 	setup_lapic();
-
-	/*
-	 * Per AMD, sync an undocumented MSR with the PSP base address.
-	 * Experiments showed that if you write to the MSR after it has
-	 * been previously programmed, it causes a general protection fault.
-	 * Also, the MSR survives warm reset and S3 cycles, so we need to
-	 * test if it was previously written before writing to it.
-	 */
-	msr_t psp_msr;
-	uint32_t psp_bar; /* Note: NDA BKDG names this 32-bit register BAR3 */
-	psp_bar = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4);
-	psp_bar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
-	psp_msr = rdmsr(0xc00110a2);
-	if (psp_msr.lo == 0) {
-		psp_msr.lo = psp_bar;
-		wrmsr(0xc00110a2, psp_msr);
-	}
 }
 
 static struct device_operations cpu_dev_ops = {