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authorMarshall Dawson <marshalldawson3rd@gmail.com>2019-06-13 15:59:38 -0600
committerMartin Roth <martinroth@google.com>2019-07-03 21:57:10 +0000
commit9df03a168fd54bc8e872448ff9fdfa30313c40ba (patch)
tree77ef54a8c620b19ea4fc35a58d88e36db53e49a0 /src/soc/amd/picasso/chip.c
parenta392b00131d1ddc8489bf24c2eb7a14300374680 (diff)
soc/amd/picasso: Remove all PSP runtime functions
Remove the mailbox call to notify the PSP that DRAM is ready. This is not supported on Family 17h. Remove the selectable SMU firmware. This is a feature of the PSP bootloader and the standard bootloader doesn't contain the ability. Clean up additional mentions of PSP within picasso. Change-Id: I8abeb4c375dbff3b438cd18ccaaf66e11c86e72e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/soc/amd/picasso/chip.c')
-rw-r--r--src/soc/amd/picasso/chip.c5
1 files changed, 0 insertions, 5 deletions
diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c
index 776f328c86..b9e98c538c 100644
--- a/src/soc/amd/picasso/chip.c
+++ b/src/soc/amd/picasso/chip.c
@@ -25,7 +25,6 @@
#include <soc/northbridge.h>
#include <soc/pci_devs.h>
#include <soc/southbridge.h>
-#include <amdblocks/psp.h>
#include <amdblocks/agesawrapper.h>
#include <amdblocks/agesawrapper_call.h>
@@ -157,10 +156,6 @@ static void earliest_ramstage(void *unused)
int s3_resume = acpi_s3_resume_allowed() &&
romstage_handoff_is_resume();
if (!s3_resume) {
- post_code(0x46);
- if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW))
- psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW2, "smu_fw2");
-
post_code(0x47);
do_agesawrapper(AMD_INIT_ENV, "amdinitenv");
} else {