diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-06-13 16:03:47 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-07-06 18:21:39 +0000 |
| commit | 78025f6c5c8a65d662c3af7d8de2ad5a59752419 (patch) | |
| tree | 7e8a577d9cd4aa0716cfe8976c585491079dcf51 /src/soc/amd/picasso/chip.c | |
| parent | fcfa35670a191d2313324fb313bac237e7a3d0c6 (diff) | |
soc/amd/picasso: Remove all AGESA references
Family 17h will not use the Arch2008 (a.k.a. v5) wrapper. Remove
all source, support functions, and comments related to AGESA.
Family 17h requires v9 which has no similarities to v5 for
integration into a host firmware. AGESA v9 support will be added
via subsequent patches into the appropriate locations.
Change-Id: Iea1a41941a0ba364a6abaaf31cc8e1145db4a236
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/picasso/chip.c')
| -rw-r--r-- | src/soc/amd/picasso/chip.c | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index b9e98c538c..65d98b127d 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -25,9 +25,6 @@ #include <soc/northbridge.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> -#include <amdblocks/agesawrapper.h> -#include <amdblocks/agesawrapper_call.h> - #include "chip.h" /* Supplied by i2c.c */ @@ -113,7 +110,6 @@ const char *soc_acpi_name(const struct device *dev) struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = domain_set_resources, - .enable_resources = domain_enable_resources, .scan_bus = pci_domain_scan_bus, .acpi_name = soc_acpi_name, }; @@ -141,7 +137,6 @@ static void soc_init(void *chip_info) static void soc_final(void *chip_info) { southbridge_final(chip_info); - fam15_finalize(chip_info); } struct chip_operations soc_amd_picasso_ops = { @@ -150,19 +145,3 @@ struct chip_operations soc_amd_picasso_ops = { .init = soc_init, .final = soc_final }; - -static void earliest_ramstage(void *unused) -{ - int s3_resume = acpi_s3_resume_allowed() && - romstage_handoff_is_resume(); - if (!s3_resume) { - post_code(0x47); - do_agesawrapper(AMD_INIT_ENV, "amdinitenv"); - } else { - /* Complete the initial system restoration */ - post_code(0x46); - do_agesawrapper(AMD_S3LATE_RESTORE, "amds3laterestore"); - } -} - -BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, earliest_ramstage, NULL); |