soc/amd/picasso: Add FSP support for including AGESA

AMD has rewritten AGESA (now at v9) for direct inclusion into UEFI
build environments.  Therefore, unlike the previous Arch2008
(a.k.a. v5), it can't be built without additional source, e.g. by
combining with EDK II, and it has no entry points for easily
building it into a legacy BIOS.

AGESA in coreboot now relies on the FSP 2.0 framework published
by Intel and uses the existing fsp2_0 driver.

* Add fsp_memory_init() to romstage.c.  Although Picasso comes out
  of reset with DRAM alive, this call is added to maximize
  compatibility and facilitate internal development.  Future work
  may look at removing it.  AGESA reports the memory map to coreboot
  via HOBs returned from fsp_memory_init().
* AGESA currently sets up MTRRs, as in most older generations.
  Take ownership back immediately before running ramstage.
* Remove cbmem initialization, as the FSP driver handles this.
* Add chipset_handle_reset() for compatibility.
* Top of memory is determined by the FSP driver checking the HOBs
  passed from AGESA.  Note that relying on the TOM register happens
  to be misleading when UMA is below 4GB.

BUG=b:147042464
TEST=Boot trembyle to payload

Change-Id: Iecb3a3f2599a8ccbc168b1d26a0271f51b71dcf0
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34423
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 3 insertions, 0 deletions

diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c
index 201afb40dd..2ab946236b 100644
--- a/src/soc/amd/picasso/chip.c
+++ b/src/soc/amd/picasso/chip.c
@@ -13,6 +13,7 @@
 #include <soc/pci_devs.h>
 #include <soc/southbridge.h>
 #include "chip.h"
+#include <fsp/api.h>
 
 /* Supplied by i2c.c */
 extern struct device_operations picasso_i2c_mmio_ops;
@@ -99,6 +100,8 @@ static void enable_dev(struct device *dev)
 
 static void soc_init(void *chip_info)
 {
+	fsp_silicon_init(acpi_is_wakeup_s3());
+
 	southbridge_init(chip_info);
 	setup_bsp_ramtop();
 }