soc/amd/picasso: Add bootblock support

The original plan for Picasso was to combine the features of bootblock
with romstage due to its unique way of coming out of reset.  Early in
development, all bootblock support was removed from the directory.
All Picasso designs will now use a bootblock as their first stage. The
reason being that it requires less invasive changes than using a hybrid
romstage.

Add a basic bootblock back to the directory, and compatible with the
design of lib/bootblock.c.  The files support RESET_VECTOR_IN_RAM
and add appropriate settings in Kconfig.  Make Makefile.inc calculates
the size and base of bootblock from known parameters.
 * Future work may attempt to streamline this further, in conjunction
   with changes in amdfwtool. See b/154957411.

BUG=b:147042464, b:153675909

Change-Id: I1d0784025f2b39f140b16f37726d4a7f36df6c6c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37490
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 66 insertions, 0 deletions

diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c
new file mode 100644
index 0000000000..8ae4db3178
--- /dev/null
+++ b/src/soc/amd/picasso/bootblock/bootblock.c
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <stdint.h>
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <soc/southbridge.h>
+#include <soc/i2c.h>
+#include <amdblocks/amd_pci_mmconf.h>
+
+asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
+{
+	enable_pci_mmconf();
+
+	bootblock_main_with_basetime(base_timestamp);
+}
+
+void bootblock_soc_early_init(void)
+{
+	sb_reset_i2c_slaves();
+	fch_pre_init();
+}
+
+void bootblock_soc_init(void)
+{
+	u32 val = cpuid_eax(1);
+	printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
+
+	fch_early_init();
+	i2c_soc_early_init();
+}
diff --git a/src/soc/amd/picasso/bootblock/pre_c.S b/src/soc/amd/picasso/bootblock/pre_c.S
new file mode 100644
index 0000000000..c478ef80bb
--- /dev/null
+++ b/src/soc/amd/picasso/bootblock/pre_c.S
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <cpu/x86/post_code.h>
+
+/*
+ * on entry:
+ *   mm0: BIST (ignored)
+ *   mm2_mm1: timestamp at bootblock_protected_mode_entry
+ */
+
+.global bootblock_pre_c_entry
+bootblock_pre_c_entry:
+	post_code(0xa0)
+
+	movl	$_eearlyram_stack, %esp
+
+	/* Align the stack and keep aligned for call to bootblock_c_entry() */
+	and	$0xfffffff0, %esp
+	sub	$8, %esp
+
+	movd	%mm2, %eax
+	pushl	%eax		/* tsc[63:32] */
+	movd	%mm1, %eax
+	pushl	%eax		/* tsc[31:0] */
+
+	post_code(0xa2)
+
+	call	bootblock_c_entry
+	/* Never reached */
+
+.halt_forever:
+	post_code(POST_DEAD_CODE)
+	hlt
+	jmp	.halt_forever