soc/amd/picasso: Update UARTs

Add a function to uart.c to ensure the right IOMux settings are
programmed for the console UART.  Update Kconfig to reflect the
new addresses.

Give the user the ability to downclock the UARTs' refclock to
1.8342MHz.

Add the abiltiy to use an APU UART at a legacy I/O address.

Update the AOAC register configuration for the two additional
UARTs.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I74579674544f0edd2c0e6c4963270b442668e62f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

3 files changed, 87 insertions, 5 deletions

diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl
index 12480c7d0f..a373a99e7d 100644
--- a/src/soc/amd/picasso/acpi/globalnvs.asl
+++ b/src/soc/amd/picasso/acpi/globalnvs.asl
@@ -55,7 +55,10 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	, 1,
 	UT0E,	1,	//        UART0, 11
 	UT1E,	1,	//        UART1, 12
-	, 14,
+	, 3,
+	UT2E,	1,	//        UART2, 16
+	, 9,
+	UT23,	1,	//        UART3, 26
 	ESPI,	1,	//        ESPI, 27
 	/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
 	Offset (0x100),
diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl
index e7975f8d94..13b9025970 100644
--- a/src/soc/amd/picasso/acpi/sb_fch.asl
+++ b/src/soc/amd/picasso/acpi/sb_fch.asl
@@ -58,7 +58,8 @@ Device (FUR0)
 	Name (_CRS, ResourceTemplate()
 	{
 		IRQ (Edge, ActiveHigh, Exclusive) { 10 }
-		Memory32Fixed (ReadWrite, 0xFEDC6000, 0x2000)
+		Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000)
+		Memory32Fixed (ReadWrite, APU_DMAC0_BASE, 0x1000)
 	})
 	Method (_STA, 0x0, NotSerialized)
 	{
@@ -71,12 +72,44 @@ Device (FUR1) {
 	Name (_UID, 0x1)
 	Name (_CRS, ResourceTemplate()
 	{
-			IRQ (Edge, ActiveHigh, Exclusive) { 11 }
-			Memory32Fixed (ReadWrite, 0xFEDC8000, 0x2000)
+		IRQ (Edge, ActiveHigh, Exclusive) { 11 }
+		Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000)
+		Memory32Fixed (ReadWrite, APU_DMAC1_BASE, 0x1000)
 	})
 	Method (_STA, 0x0, NotSerialized)
 	{
-			Return (0x0F)
+		Return (0x0F)
+	}
+}
+
+Device (FUR2)
+{
+	Name (_HID, "AMD0020")
+	Name (_UID, 0x0)
+	Name (_CRS, ResourceTemplate()
+	{
+		IRQ (Edge, ActiveHigh, Exclusive) { 15 }
+		Memory32Fixed (ReadWrite, APU_UART2_BASE, 0x1000)
+		Memory32Fixed (ReadWrite, APU_DMAC2_BASE, 0x1000)
+	})
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
+
+Device (FUR3) {
+	Name (_HID, "AMD0020")
+	Name (_UID, 0x1)
+	Name (_CRS, ResourceTemplate()
+	{
+		IRQ (Edge, ActiveHigh, Exclusive) { 5 }
+		Memory32Fixed (ReadWrite, APU_UART3_BASE, 0x1000)
+		Memory32Fixed (ReadWrite, APU_DMAC3_BASE, 0x1000)
+	})
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
 	}
 }
 
diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
index 5e16fefaa5..bd340dd4bb 100644
--- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
+++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
@@ -236,9 +236,23 @@ Field( SMIC, ByteAcc, NoLock, Preserve) {
 	offset (0x1e59), /* UART1 D3 State */
 	U1DS, 3,
 
+	offset (0x1e60), /* UART2 D3 Control */
+	U2TD, 2,
+	, 1,
+	U2PD, 1,
+	offset (0x1e61), /* UART2 D3 State */
+	U2DS, 3,
+
 	offset (0x1e71), /* SD D3 State */
 	SDDS, 3,
 
+	offset (0x1e74), /* UART3 D3 Control */
+	U3TD, 2,
+	, 1,
+	U3PD, 1,
+	offset (0x1e75), /* UART3 D3 State */
+	U3DS, 3,
+
 	offset (0x1e80), /* Shadow Register Request */
 	, 15,
 	RQ15, 1,
@@ -375,6 +389,22 @@ Method(FDDC, 2, Serialized)
 					Store(U1DS, Local0)
 				}
 			}
+			Case(16) {
+				Store(0x00, U2TD)
+				Store(One, U2PD)
+				Store(U2DS, Local0)
+				while(LNotEqual(Local0,0x7)) {
+					Store(U2DS, Local0)
+				}
+			}
+			Case(26) {
+				Store(0x00, U3TD)
+				Store(One, U3PD)
+				Store(U3DS, Local0)
+				while(LNotEqual(Local0,0x7)) {
+					Store(U3DS, Local0)
+				}
+			}
 		}
 	} else {
 		/* put device into D3cold */
@@ -427,6 +457,22 @@ Method(FDDC, 2, Serialized)
 				}
 				Store(0x03, U1TD)
 			}
+			Case(16) {
+				Store(Zero, U2PD)
+				Store(U2DS, Local0)
+				while(LNotEqual(Local0,0x0)) {
+					Store(U2DS, Local0)
+				}
+				Store(0x03, U2TD)
+			}
+			Case(26) {
+				Store(Zero, U3PD)
+				Store(U3DS, Local0)
+				while(LNotEqual(Local0,0x0)) {
+					Store(U3DS, Local0)
+				}
+				Store(0x03, U3TD)
+			}
 		}
 		if(LEqual(I1TD, 3)) {
 			if(LEqual(I2TD, 3)) {