diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-07-01 10:53:40 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-07-03 21:48:52 +0000 |
| commit | 7997f1ff88d6154890b2489c93548f266ae6b8a9 (patch) | |
| tree | 810efcd701b1394ca8146b677f79790f602dd86d /src/soc/amd/picasso/acpi | |
| parent | fa4a74b098731bf3e0979c20a65fa883bf4c57f3 (diff) | |
soc/amd/picasso: Remove SD controller
Change-Id: Ie9cf361ed0caba9c73727453c4a503557edc854d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/picasso/acpi')
| -rw-r--r-- | src/soc/amd/picasso/acpi/globalnvs.asl | 4 | ||||
| -rw-r--r-- | src/soc/amd/picasso/acpi/sb_pci0_fch.asl | 46 |
2 files changed, 1 insertions, 49 deletions
diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index cdb32cc0d3..cc264e6f85 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -58,9 +58,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) UT1E, 1, // UART1, 12 , 2, ST_E, 1, // SATA, 15 - , 8, - SD_E, 1, // SD, 24 - , 2, + , 11, ESPI, 1, // ESPI, 27 /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 8cdb4d2750..206fdfd0e1 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -53,21 +53,6 @@ Device(SBUS) { /* 0:14.3 - LPC */ #include <soc/amd/common/acpi/lpc.asl> -/* 0:14.7 - SD Controller */ -Device(SDCN) { - Name(_ADR, 0x00140007) - - Method(_PS0) { - FDDC(24, 0) - } - Method(_PS3) { - FDDC(24, 3) - } - Method(_PSC) { - Return(SDTD) - } -} /* end SDCN */ - Name(CRES, ResourceTemplate() { /* Set the Bus number and Secondary Bus number for the PCI0 device * The Secondary bus range for PCI0 lets the system @@ -272,15 +257,6 @@ Field( SMIC, ByteAcc, NoLock, Preserve) { offset (0x1e6f), /* USB3 D3 State */ U3DS, 3, - offset (0x1e70), /* SD D3 Control */ - SDTD, 2, - , 1, - SDPD, 1, - , 1, - , 1, - SDRT, 1, - SDSC, 1, - offset (0x1e71), /* SD D3 State */ SDDS, 3, @@ -421,14 +397,6 @@ Method(FDDC, 2, Serialized) } } /* todo Case(15) { STD0()} */ /* SATA */ - Case(24) { /* SD */ - Store(0x00, SDTD) - Store(One, SDPD) - Store(SDDS, Local0) - while(LNotEqual(Local0,0x7)) { - Store(SDDS, Local0) - } - } } } else { /* put device into D3cold */ @@ -482,20 +450,6 @@ Method(FDDC, 2, Serialized) Store(0x03, U1TD) } /* todo Case(15) { STD3()} */ /* SATA */ - Case(24) { /* SD */ - Store(Zero, SDPD) - Store(SDDS, Local0) - while(LNotEqual(Local0,0x0)) { - Store(SDDS, Local0) - } - Store(0x03, SDTD) - } - } - /* Turn off Power */ - if(LEqual(I0TD, 3)) { - if(LEqual(SATD, 3)) { - if(LEqual(SDTD, 3)) { Store(Zero, PG1A) } - } } if(LEqual(I1TD, 3)) { if(LEqual(I2TD, 3)) { |