diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2020-07-13 16:10:34 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-07-15 08:38:43 +0000 |
| commit | 742abd3daf6be57de2df5002b8985ad36884c959 (patch) | |
| tree | cdfae09c0acf514a7b26c5256742e88f32ed281e /src/soc/amd/picasso/acpi/pcie.asl | |
| parent | 1aa5cff70908a18b1bd0fd41b2e2ad7014cf9813 (diff) | |
soc/amd/picasso/acpi: Delete unused and invalid OperationRegions
0xc50, 0xc52, 0xc6f don't exist on Picasso. The PCI config space
registers define SATA and OHCI which are at the wrong bus locations.
I just remove the whole section since it's not used. We never access the
PCIe Error region, or the PM2 region either.
BUG=b:153001807, b:154756391
TEST=Build Trembyle
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I98aee09770f1df9f553c94580c1ee00c06a9cec1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/amd/picasso/acpi/pcie.asl')
| -rw-r--r-- | src/soc/amd/picasso/acpi/pcie.asl | 48 |
1 files changed, 0 insertions, 48 deletions
diff --git a/src/soc/amd/picasso/acpi/pcie.asl b/src/soc/amd/picasso/acpi/pcie.asl index 954c536539..e88026781d 100644 --- a/src/soc/amd/picasso/acpi/pcie.asl +++ b/src/soc/amd/picasso/acpi/pcie.asl @@ -64,54 +64,6 @@ IUA3, 0x00000008, /* Index 0xF9: UART3 */ } - /* PCI Error control register */ - OperationRegion(PERC, SystemIO, 0x00000c14, 0x00000001) - Field(PERC, ByteAcc, NoLock, Preserve) { - SENS, 0x00000001, - PENS, 0x00000001, - SENE, 0x00000001, - PENE, 0x00000001, - } - - /* Client Management index/data registers */ - OperationRegion(CMT, SystemIO, 0x00000c50, 0x00000002) - Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, - /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, - } - - /* GPM Port register */ - OperationRegion(GPT, SystemIO, 0x00000c52, 0x00000001) - Field(GPT, ByteAcc, NoLock, Preserve) { - GPB0,1, - GPB1,1, - GPB2,1, - GPB3,1, - GPB4,1, - GPB5,1, - GPB6,1, - GPB7,1, - } - - /* Flash ROM program enable register */ - OperationRegion(FRE, SystemIO, 0x00000c6F, 0x00000001) - Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, - FLRE, 0x00000001, - } - - /* PM2 index/data registers */ - OperationRegion(PM2R, SystemIO, 0x00000Cd0, 0x00000002) - Field(PM2R, ByteAcc, NoLock, Preserve) { - PM2I, 0x00000008, - PM2D, 0x00000008, - } - /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ OperationRegion(PIOR, SystemIO, 0x00000Cd6, 0x00000002) Field(PIOR, ByteAcc, NoLock, Preserve) { |