diff options
author | Raul E Rangel <rrangel@chromium.org> | 2020-05-11 16:26:35 -0600 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-13 08:36:46 +0000 |
commit | 789aefc2272c2ffb3ca2c9380ccdc1a2288f2534 (patch) | |
tree | d7d68ddda073989308477c304d58a15439ca3ac8 /src/soc/amd/picasso/Makefile.inc | |
parent | 658a2913a5bbe9c638c0d069ea663ecb77b490b0 (diff) |
soc/amd/picasso: Mark FCH MMIO addresses as non-posted
Immediately following FSP-S, update the data fabric routing
registers to make the region between HPET and LAPIC as non-posted.
If AGESA is modified to do this, we can delete data_fabric_util.c. If
AGESA is modified to not program the registers, then we can simplify
data_fabric_set_mmio_np().
BUG=b:147042464, b:156296146
TEST=boot trembyle
Change-Id: Idbafaac158f5a4c533d2d88db79bb4d6244e5355
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41268
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso/Makefile.inc')
-rw-r--r-- | src/soc/amd/picasso/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 0e5cdf54ce..e015fbe057 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -44,6 +44,7 @@ verstage-y += tsc_freq.c ramstage-y += i2c.c ramstage-y += chip.c ramstage-y += cpu.c +ramstage-y += data_fabric_util.c ramstage-y += mca.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += gpio.c |