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authorFelix Held <felix-coreboot@felixheld.de>2021-02-08 20:02:58 +0100
committerFelix Held <felix-coreboot@felixheld.de>2021-02-12 14:39:53 +0000
commit1a39aa01d118a0d917cbe326bd6cfdfa9bbcf0bf (patch)
treebaaeb8ca35004fe808012fcdb9d0d0f60a8512da /src/soc/amd/picasso/Makefile.inc
parent9d5e724010384418f32183dfafeb25305f05652a (diff)
soc/amd/picasso: move bert_reserved_region to common/block/cpu/noncar
The same functionality will eventually be needed on Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib49124c2c774ad3352ea2f7d8d827388029be041 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/picasso/Makefile.inc')
-rw-r--r--src/soc/amd/picasso/Makefile.inc2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc
index e92de1f588..99e2da1040 100644
--- a/src/soc/amd/picasso/Makefile.inc
+++ b/src/soc/amd/picasso/Makefile.inc
@@ -23,7 +23,6 @@ romstage-y += i2c.c
romstage-y += romstage.c
romstage-y += gpio.c
romstage-y += reset.c
-romstage-y += memmap.c
romstage-y += uart.c
romstage-y += mrc_cache.c
@@ -45,7 +44,6 @@ ramstage-y += fch.c
ramstage-y += reset.c
ramstage-y += acp.c
ramstage-y += sata.c
-ramstage-y += memmap.c
ramstage-y += uart.c
ramstage-y += finalize.c
ramstage-y += soc_util.c