soc/amd/picasso: Add bootblock support

The original plan for Picasso was to combine the features of bootblock
with romstage due to its unique way of coming out of reset.  Early in
development, all bootblock support was removed from the directory.
All Picasso designs will now use a bootblock as their first stage. The
reason being that it requires less invasive changes than using a hybrid
romstage.

Add a basic bootblock back to the directory, and compatible with the
design of lib/bootblock.c.  The files support RESET_VECTOR_IN_RAM
and add appropriate settings in Kconfig.  Make Makefile.inc calculates
the size and base of bootblock from known parameters.
 * Future work may attempt to streamline this further, in conjunction
   with changes in amdfwtool. See b/154957411.

BUG=b:147042464, b:153675909

Change-Id: I1d0784025f2b39f140b16f37726d4a7f36df6c6c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37490
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 17 insertions, 11 deletions

diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc
index d31e518edc..b04e1e9217 100644
--- a/src/soc/amd/picasso/Makefile.inc
+++ b/src/soc/amd/picasso/Makefile.inc
@@ -11,6 +11,15 @@ subdirs-y += ../../../cpu/x86/mtrr
 subdirs-y += ../../../cpu/x86/pae
 subdirs-y += ../../../cpu/x86/smm
 
+bootblock-y += bootblock/pre_c.S
+bootblock-y += bootblock/bootblock.c
+bootblock-y += southbridge.c
+bootblock-y += i2c.c
+bootblock-$(CONFIG_PICASSO_UART) += uart.c
+bootblock-y += tsc_freq.c
+bootblock-y += gpio.c
+bootblock-y += smi_util.c
+
 romstage-y += i2c.c
 romstage-y += romstage.c
 romstage-y += gpio.c
@@ -29,12 +38,6 @@ verstage-y += pmutil.c
 verstage-$(CONFIG_PICASSO_UART) += uart.c
 verstage-y += tsc_freq.c
 
-postcar-y += monotonic_timer.c
-postcar-$(CONFIG_PICASSO_UART) += uart.c
-postcar-y += memmap.c
-postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c
-postcar-y += tsc_freq.c
-
 ramstage-y += i2c.c
 ramstage-y += chip.c
 ramstage-y += cpu.c
@@ -179,8 +182,12 @@ PSP_APOB_BASE=$(CONFIG_PSP_APOB_DESTINATION)
 
 # type = 0x62
 PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img
-PSP_BIOSBIN_DEST=$(CONFIG_ROMSTAGE_ADDR)
-PSP_BIOSBIN_SIZE=$(CONFIG_RAM_RESET_VECTOR_STAGE_SIZE)
+PSP_ELF_FILE=$(objcbfs)/bootblock.elf
+# TODO(b/154957411): Refactor amdfwtool to extract the address and size from
+# the elf file.
+PSP_BIOSBIN_SIZE=$(CONFIG_C_ENV_BOOTBLOCK_SIZE)
+# This address must match the BOOTBLOCK logic in arch/x86/memlayout.ld.
+PSP_BIOSBIN_DEST=$(shell printf "%x" $(call int-subtract, $(call int-add, $(CONFIG_X86_RESET_VECTOR) 0x10) $(PSP_BIOSBIN_SIZE)))
 
 # type = 0x63
 ifeq ($(CONFIG_HAVE_ACPI_RESUME),y)
@@ -368,11 +375,10 @@ $(obj)/amdfw.rom:	$(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \
 		--location $(shell printf "0x%x" $(PICASSO_FWM_POSITION)) \
 		--output	$@
 
-USE_BIOS_FILE=$(obj)/cbfs/fallback/romstage.elf
-$(PSP_BIOSBIN_FILE): $(obj)/cbfs/fallback/romstage.elf $(AMDCOMPRESS)
+$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS)
 	rm -f $@
 	@printf "    AMDCOMPRS  $(subst $(obj)/,,$(@))\n"
-	$(AMDCOMPRESS) --infile $(USE_BIOS_FILE) --outfile $@ --compress \
+	$(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \
 		--maxsize $(PSP_BIOSBIN_SIZE)
 
 ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)