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| author | Furquan Shaikh <furquan@google.com> | 2020-06-08 12:30:40 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-10 18:45:56 +0000 |
| commit | f9be2d10c9a5e377304944de33357ae1ec9bdb7b (patch) | |
| tree | 2cc7fe06633821a142880f6d62e848ec9482f651 /src/soc/amd/picasso/Kconfig | |
| parent | dbce8ba05afa6febbcb5932a03e97e1d4cd982d9 (diff) | |
soc/amd/picasso: Enable APOB/MRC training data cache
Picasso doesn't really make use of the common mrc_cache driver because
of the PSP/ABL requirements for APOB NV data. The APOB NV data
gets consumed by PSP/ABLs before x86 comes out of reset. Hence, we cannot
really add any metadata to this saved data or use multiple slots as
done by the default MRC cache driver
(CACHE_MRC_SETTINGS). Additionally, FSP-M requires access to this APOB
NV data which coreboot needs to pass in from different locations
depending upon boot mode:
1. Non-S3 boot: PSP/ABLs store APOB NV data in DRAM at predetermined
location which is present in BIOS directory table.
2. S3 boot: PSP/ABLs do not store APOB NV data in DRAM.
Thus, coreboot needs to set FSP-M UPD NvsBufferPtr as the DRAM
location in non-S3 boot and the address of RW_MRC_CACHE on SPI flash
in case of S3 resume.
This change enables MRC cache support in Picasso in order to meet the
above requirements.
1. NvsBufferPtr is set based on boot mode.
2. APOB NV data is not stashed to CBMEM. Instead it is written right
away to SPI flash in romstage.
BUG=b:155990176
Change-Id: I8661a4cf2d34502967e936bf22a13f6f1b88e544
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/picasso/Kconfig')
| -rw-r--r-- | src/soc/amd/picasso/Kconfig | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index e3d145d80f..5ba0c1b2e0 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -53,7 +53,6 @@ config CPU_SPECIFIC_OPTIONS select FSP_COMPRESS_FSP_S_LZMA select FSP_USES_CB_STACK select UDK_2017_BINDING - select CACHE_MRC_SETTINGS select HAVE_CF9_RESET config PRERAM_CBMEM_CONSOLE_SIZE @@ -303,17 +302,6 @@ config PSP_APOB_DRAM_ADDRESS Location in DRAM where the PSP will copy the AGESA PSP Output Block. -# This value is currently the same as the default defined in -# drivers/mrc_cache/Kconfig. We do this in in case the default -# changes. The PSP requires this value to be 64KiB. -config MRC_SETTINGS_CACHE_SIZE - hex - default 0x10000 - help - Size of flash area used to save APOB NV data which occupies the - RW_MRC_CACHE region. Make this granularity the flash device can - erase. - config USE_PSPSCUREOS bool default y |