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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2020-01-21 14:53:45 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-04-18 15:54:33 +0000 |
| commit | 901cb9ca46b334aeb0134fa19cc87b445420c7fa (patch) | |
| tree | 49041319f49b998515b6146286cf0780a5746b80 /src/soc/amd/picasso/Kconfig | |
| parent | 4fc59af03d0d76caa0b8497ea894f360c15c1a39 (diff) | |
soc/amd/picasso: Move BERT region to cbmem
Allocate storage for the BERT reserved memory in cbmem, and add it in
response to a romstage hook. Add a Kconfig option for adjusting the
size reserved. This is different from the Stoney Ridge implementation
where it was intentionally oversized to ease MTRR use and to keep TSEG
aligned.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4759154d394a8f5b35c0ef0a15994bbef25492e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38694
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso/Kconfig')
| -rw-r--r-- | src/soc/amd/picasso/Kconfig | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 842ba0cd37..4759f01ecc 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -199,6 +199,13 @@ config ACPI_BERT ACPI Boot Error Record Table. This option reserves an 8MB region for building the error structures. +config ACPI_BERT_SIZE + hex + default 0x4000 + help + Specify the amount of DRAM reserved for gathering the data used to + generate the ACPI table. + config RO_REGION_ONLY string depends on CHROMEOS |