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authorMarshall Dawson <marshalldawson3rd@gmail.com>2020-09-04 12:07:27 -0600
committerMarshall Dawson <marshalldawson3rd@gmail.com>2020-09-10 12:37:45 +0000
commit39c64b0bdd04a84bf206be5a94ceb1d685e9e1a8 (patch)
treee8a475836ed5567c464edb026d6ca9ee48b4e48c /src/soc/amd/picasso/Kconfig
parent39a8040ddc551306d823d52a459fdb5dd717b2fe (diff)
soc/amd/picasso: Assign IOAPIC IDs, GNB APIC base with FSP
Add Kconfig symbols for the FCH and GNB IOAPIC IDs, then pass the info to FSP to keep it in sync with coreboot. Do the same for the northbridge's IOAPIC base address. Use the new values where needed, and reserve the resources consumed by the GNB IOAPIC. BUG=b:167421913, b:166519072 TEST=Boot Morphius and verify settings BRANCH=Zork Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I57d3d6b2ebd8b5d511dbcb4324ea065cc3111a2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/45115 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso/Kconfig')
-rw-r--r--src/soc/amd/picasso/Kconfig18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index ec5ff76c72..29ebc6dd2b 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -243,6 +243,24 @@ config EHCI_BAR
hex
default 0xfef00000
+config PICASSO_FCH_IOAPIC_ID
+ hex
+ default 0x8
+ help
+ The Picasso APU has two IOAPICs, one in the FCH and one in the
+ northbridge. Set this value for the intended ID to assign to the
+ FCH IOAPIC. The value should be >= MAX_CPUS and different from
+ the GNB's IOAPIC_ID.
+
+config PICASSO_GNB_IOAPIC_ID
+ hex
+ default 0x9
+ help
+ The Picasso APU has two IOAPICs, one in the FCH and one in the
+ northbridge. Set this value for the intended ID to assign to the
+ GNB IOAPIC. The value should be >= MAX_CPUS and different from
+ the FCH's IOAPIC_ID.
+
config SERIRQ_CONTINUOUS_MODE
bool
default n