diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-12-05 00:41:05 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-12-06 16:01:18 +0000 |
| commit | f5b09dbe1840e2ba2bbc9b2c6225e838cb7a32b9 (patch) | |
| tree | 3f3224e9ceb971d762207c1c733e37b4d930e10c /src/soc/amd/phoenix/chipset.cb | |
| parent | 3e306d48cd9f862e55e4458da0eb2c6a606cb796 (diff) | |
soc/amd/*/chipset.cb: don't call dummy device functions host bridges
Function 0 of the devices that have the bridges to other buses are dummy
functions that can be left enabled to not have to shuffle around the
device function numbers when the first PCI bridge on those devices isn't
enabled. Those dummy device functions are however not PCI host bridges,
so change the comments from 'Dummy Host Bridge' to 'Dummy device
function'.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Nico Huber <nico.h@gmx.de>
Change-Id: Ibddfdf558d84bc44434d718b86f41bd06044b22a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/phoenix/chipset.cb')
| -rw-r--r-- | src/soc/amd/phoenix/chipset.cb | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/amd/phoenix/chipset.cb b/src/soc/amd/phoenix/chipset.cb index 12bb2fe659..08ee8c20cf 100644 --- a/src/soc/amd/phoenix/chipset.cb +++ b/src/soc/amd/phoenix/chipset.cb @@ -9,14 +9,14 @@ chip soc/amd/phoenix device pci 00.0 alias gnb on ops phoenix_root_complex_operations end device pci 00.2 alias iommu off ops amd_iommu_ops end - device pci 01.0 on end # Dummy Host Bridge, do not disable + device pci 01.0 on end # Dummy device function, do not disable # The PCIe GPP aliases in this SoC match the device and function numbers device pci 01.1 alias gpp_bridge_1_1 hidden ops amd_external_pcie_gpp_ops end device pci 01.2 alias gpp_bridge_1_2 hidden ops amd_external_pcie_gpp_ops end device pci 01.3 alias gpp_bridge_1_3 hidden ops amd_external_pcie_gpp_ops end device pci 01.4 alias gpp_bridge_1_4 hidden ops amd_external_pcie_gpp_ops end - device pci 02.0 on end # Dummy Host Bridge, do not disable + device pci 02.0 on end # Dummy device function, do not disable # The PCIe GPP aliases in this SoC match the device and function numbers device pci 02.1 alias gpp_bridge_2_1 hidden ops amd_external_pcie_gpp_ops end device pci 02.2 alias gpp_bridge_2_2 hidden ops amd_external_pcie_gpp_ops end @@ -25,13 +25,13 @@ chip soc/amd/phoenix device pci 02.5 alias gpp_bridge_2_5 hidden ops amd_external_pcie_gpp_ops end device pci 02.6 alias gpp_bridge_2_6 hidden ops amd_external_pcie_gpp_ops end - device pci 03.0 on end # Dummy Host Bridge, do not disable + device pci 03.0 on end # Dummy device function, do not disable device pci 03.1 alias usb4_pcie_bridge_0 off end - device pci 04.0 on end # Dummy Host Bridge, do not disable + device pci 04.0 on end # Dummy device function, do not disable device pci 04.1 alias usb4_pcie_bridge_1 off end - device pci 08.0 on end # Dummy Host Bridge, do not disable + device pci 08.0 on end # Dummy device function, do not disable device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A ops amd_internal_pcie_gpp_ops device pci 0.0 alias gfx off ops amd_graphics_ops end # Internal GPU (GFX) |