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authorFelix Held <felix-coreboot@felixheld.de>2024-02-01 20:13:09 +0100
committerFelix Held <felix-coreboot@felixheld.de>2024-02-02 20:37:07 +0000
commitcbbb09b685eeb74afeb0fb9f14f7694fcd0654f0 (patch)
treed3ac5905871c8e46d5b64adf23b6a49a6836c5b1 /src/soc/amd/phoenix/Makefile.mk
parent0d595302da57fb7d73a6e6efd9b89a887d8f5c90 (diff)
soc/amd/phoenix: add get_pci_routing_table stub for non-FSP case
In the FSP case we get this info via a HOB. It's currently unclear if we'll get a data structure for this from openSIL or if we'll end up being able to just read the configuration fro the hardware, so add a get_pci_routing_table stub for now to be able to build. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5003e287d6a3a9320922beaffff8a3a846531e14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/phoenix/Makefile.mk')
-rw-r--r--src/soc/amd/phoenix/Makefile.mk1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/phoenix/Makefile.mk b/src/soc/amd/phoenix/Makefile.mk
index 9c775cc432..be0a02296f 100644
--- a/src/soc/amd/phoenix/Makefile.mk
+++ b/src/soc/amd/phoenix/Makefile.mk
@@ -32,6 +32,7 @@ ramstage-$(CONFIG_SOC_AMD_PHOENIX_FSP) += fsp_s_params.c
ramstage-y += graphics.c
ramstage-y += mca.c
ramstage-y += memmap.c
+ramstage-$(CONFIG_SOC_AMD_PHOENIX_OPENSIL) += pci_irq_routing.c
ramstage-y += root_complex.c
ramstage-y += soc_util.c
ramstage-y += xhci.c