soc/amd/mendocino: drop code for non-existing eMMC controller

Mendocino and Rembrandt don't have an eMMC controller and also don't
have GPIO pins that eMMC signals can be multiplexed on, so drop the eMMC
related code from Mendocino.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib8ec49a7084bdd62e480baee75a280fde8b13d01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>

8 files changed, 1 insertions, 17 deletions

diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig
index 91fd57d326..41861eee3e 100644
--- a/src/soc/amd/mendocino/Kconfig
+++ b/src/soc/amd/mendocino/Kconfig
@@ -45,7 +45,6 @@ config SOC_AMD_REMBRANDT_BASE
 	select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
 	select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H
 	select SOC_AMD_COMMON_BLOCK_DATA_FABRIC
-	select SOC_AMD_COMMON_BLOCK_EMMC
 	select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES
 	select SOC_AMD_COMMON_BLOCK_GRAPHICS
 	select SOC_AMD_COMMON_BLOCK_HAS_ESPI
diff --git a/src/soc/amd/mendocino/acpi/pci_int_defs.asl b/src/soc/amd/mendocino/acpi/pci_int_defs.asl
index 6d194036d4..1b40e7a27c 100644
--- a/src/soc/amd/mendocino/acpi/pci_int_defs.asl
+++ b/src/soc/amd/mendocino/acpi/pci_int_defs.asl
@@ -20,9 +20,6 @@ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
 	PIRG, 0x00000008,	/* Index 6: INTG */
 	PIRH, 0x00000008,	/* Index 7: INTH */
 
-	Offset (0x43),
-	PMMC, 0x00000008,	/* Index 0x43: eMMC */
-
 	Offset (0x62),
 	PGPI, 0x00000008,	/* Index 0x62: GPIO */
 
@@ -49,9 +46,6 @@ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
 	IORG, 0x00000008,	/* Index 0x86: INTG */
 	IORH, 0x00000008,	/* Index 0x87: INTH */
 
-	Offset (0xC3),
-	IMMC, 0x00000008,	/* Index 0xC3: eMMC */
-
 	Offset (0xE2),
 	IGPI, 0x00000008,	/* Index 0xE2: GPIO */
 
diff --git a/src/soc/amd/mendocino/chipset_mendocino.cb b/src/soc/amd/mendocino/chipset_mendocino.cb
index c1da13cd3a..691cca03d9 100644
--- a/src/soc/amd/mendocino/chipset_mendocino.cb
+++ b/src/soc/amd/mendocino/chipset_mendocino.cb
@@ -90,5 +90,4 @@ chip soc/amd/mendocino
 	device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end
 	device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end
 	device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end
-	device mmio 0xfedd5000 alias emmc off ops amd_emmc_mmio_ops end
 end
diff --git a/src/soc/amd/mendocino/chipset_rembrandt.cb b/src/soc/amd/mendocino/chipset_rembrandt.cb
index fe97cf8f7d..fd31efeb8e 100644
--- a/src/soc/amd/mendocino/chipset_rembrandt.cb
+++ b/src/soc/amd/mendocino/chipset_rembrandt.cb
@@ -93,5 +93,4 @@ chip soc/amd/mendocino
 	device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end
 	device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end
 	device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end
-	device mmio 0xfedd5000 alias emmc off ops amd_emmc_mmio_ops end
 end
diff --git a/src/soc/amd/mendocino/fch.c b/src/soc/amd/mendocino/fch.c
index 5edbcc6072..772cca0600 100644
--- a/src/soc/amd/mendocino/fch.c
+++ b/src/soc/amd/mendocino/fch.c
@@ -52,7 +52,6 @@ static const struct irq_idx_name irq_association[] = {
 	{ PIRQ_GPIOA,	"GPIOa" },
 	{ PIRQ_GPIOB,	"GPIOb" },
 	{ PIRQ_GPIOC,	"GPIOc" },
-	{ PIRQ_EMMC,	"eMMC" },
 	{ PIRQ_GPP0,	"GPP0" },
 	{ PIRQ_GPP1,	"GPP1" },
 	{ PIRQ_GPP2,	"GPP2" },
diff --git a/src/soc/amd/mendocino/include/soc/amd_pci_int_defs.h b/src/soc/amd/mendocino/include/soc/amd_pci_int_defs.h
index 35e0d90c14..fec7aef4e0 100644
--- a/src/soc/amd/mendocino/include/soc/amd_pci_int_defs.h
+++ b/src/soc/amd/mendocino/include/soc/amd_pci_int_defs.h
@@ -38,9 +38,7 @@
 #define PIRQ_GPIOA	0x21	/* GPIOa from PAD_FANIN0 */
 #define PIRQ_GPIOB	0x22	/* GPIOb from PAD_FANOUT0 */
 #define PIRQ_GPIOC	0x23	/* GPIOc no IRQ connected */
-/* 0x24-0x42 reserved */
-#define PIRQ_EMMC	0x43	/* eMMC */
-/* 0x44-0x4f reserved */
+/* 0x24-0x4f reserved */
 #define PIRQ_GPP0	0x50	/* GPPInt0 */
 #define PIRQ_GPP1	0x51	/* GPPInt1 */
 #define PIRQ_GPP2	0x52	/* GPPInt2 */
diff --git a/src/soc/amd/mendocino/include/soc/aoac_defs.h b/src/soc/amd/mendocino/include/soc/aoac_defs.h
index 46fb318aea..5dcca03abf 100644
--- a/src/soc/amd/mendocino/include/soc/aoac_defs.h
+++ b/src/soc/amd/mendocino/include/soc/aoac_defs.h
@@ -18,6 +18,5 @@
 #define FCH_AOAC_DEV_UART4		20
 #define FCH_AOAC_DEV_UART3		26
 #define FCH_AOAC_DEV_ESPI		27
-#define FCH_AOAC_DEV_EMMC		28
 
 #endif /* AMD_MENDOCINO_AOAC_DEFS_H */
diff --git a/src/soc/amd/mendocino/include/soc/iomap.h b/src/soc/amd/mendocino/include/soc/iomap.h
index 1e1120cfbe..859dfd5e9c 100644
--- a/src/soc/amd/mendocino/include/soc/iomap.h
+++ b/src/soc/amd/mendocino/include/soc/iomap.h
@@ -34,9 +34,6 @@
 #define APU_DMAC4_BASE			0xfedd0000
 #define APU_UART4_BASE			0xfedd1000
 
-#define APU_EMMC_BASE			0xfedd5000
-#define APU_EMMC_CONFIG_BASE		0xfedd5800
-
 #endif /* ENV_X86 */
 
 #define FLASH_BASE_ADDR			((0xffffffff - CONFIG_ROM_SIZE) + 1)