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authorFelix Held <felix-coreboot@felixheld.de>2023-03-23 23:44:03 +0100
committerFelix Held <felix-coreboot@felixheld.de>2023-03-27 12:02:21 +0000
commit23a398e001b55950f7759aa7ffa2ec966e2ea917 (patch)
tree87e4cf413dd987a8b3b6f1cee6211cdd28bda6bd /src/soc/amd/mendocino/include
parentfd5d26522c021c8f7a3242609f3b54cf209a8767 (diff)
soc/amd: introduce and use get_uvolts_from_vid for SVI2 and SVI3
Instead of implementing the conversion from the raw serial voltage ID value to the voltage in microvolts in every SoC, introduce the SOC_AMD_COMMON_BLOCK_SVI[2,3] Kconfig options for the SoC to select the correct version, implement get_uvolts_from_vid for both cases and only include the selected implementation in the build. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I344641217e6e4654fd281d434b88e346e0482f57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73995 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/mendocino/include')
-rw-r--r--src/soc/amd/mendocino/include/soc/msr.h4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/soc/amd/mendocino/include/soc/msr.h b/src/soc/amd/mendocino/include/soc/msr.h
index cb03425d2a..b83997a029 100644
--- a/src/soc/amd/mendocino/include/soc/msr.h
+++ b/src/soc/amd/mendocino/include/soc/msr.h
@@ -23,10 +23,6 @@ union pstate_msr {
#define PSTATE_DEF_FREQ_DIV_MAX 0x3E
#define PSTATE_DEF_CORE_FREQ_BASE 25
-/* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */
-#define SERIAL_VID_3_DECODE_MICROVOLTS 5000
-#define SERIAL_VID_3_BASE_MICROVOLTS 245000L
-
#define MSR_CPPC_CAPABILITY_1 0xc00102b0
#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24
#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16