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authorFelix Held <felix-coreboot@felixheld.de>2024-02-01 20:25:02 +0100
committerFelix Held <felix-coreboot@felixheld.de>2024-02-02 20:37:18 +0000
commit2911823289d6469970f46514193705c863c42113 (patch)
tree27667ced0bec69e4640e2f6a18aa8d4376f35b0d /src/soc/amd/mendocino/fch.c
parentcbbb09b685eeb74afeb0fb9f14f7694fcd0654f0 (diff)
soc/amd/phoenix/fch: only call gpp_clk_setup in FSP case
The configuration of the PCIe clock generators in the FCH was moved from the FSP to coreboot, since all registers are documented. This initialization is however tightly integrated in the rest of the PCIe init code inside the reference code. In the FSP case, this code was manually removed. openSIL will do that part of the initialization so that there's no coreboot-specific change needed in openSIL. This will also avoid the problems caused by mismatching configurations done by the coreboot code and the PCIe init part of the reference code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6d64285a301ade6860c07e62dcb1a718e7a96644 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/mendocino/fch.c')
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