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authorTim Van Patten <timvp@google.com>2022-08-29 12:11:27 -0600
committerFelix Held <felix-coreboot@felixheld.de>2022-09-12 12:42:04 +0000
commitb4b85ebf606b61e4d78aec0742d0652654049717 (patch)
tree68e238babe77fb5f5b36f504fd4583e26b4193d7 /src/soc/amd/mendocino/chip.h
parentc8a86954f3336da19c96320b6c695ea4a25a8990 (diff)
soc/amd: Remove unsupported DPTC tablet mode settings
The following boards are setting DTPC tablet mode values without corresponding device tree values, meaning they are effectively setting "random" values for tablet mode: 1. Cezanne 2. Mendocino The device tree has tablet mode disabled, so the code should never be exercised, but this CL removes it entirely to cleanup "dead" code. BRANCH=none BUG=b:217911928 TEST=Build nipperkin TEST=Boot skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: Ide96f255b69670d1b4c37ca2f94cc3504a958b57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/soc/amd/mendocino/chip.h')
-rw-r--r--src/soc/amd/mendocino/chip.h9
1 files changed, 1 insertions, 8 deletions
diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h
index 654294d186..7b33340736 100644
--- a/src/soc/amd/mendocino/chip.h
+++ b/src/soc/amd/mendocino/chip.h
@@ -82,14 +82,7 @@ struct soc_amd_mendocino_config {
uint32_t telemetry_vddcrsocfull_scale_current_mA;
uint32_t telemetry_vddcrsocoffset;
- /* Enable dptc tablet mode */
- bool dptc_tablet_mode_enable;
-
- /* STAPM Configuration for tablet mode */
- uint32_t fast_ppt_limit_tablet_mode_mW;
- uint32_t slow_ppt_limit_tablet_mode_mW;
- uint32_t sustained_power_limit_tablet_mode_mW;
- uint32_t thermctl_limit_tablet_mode_degreeC;
+ bool dptc_enable;
/* The array index is the general purpose PCIe clock output number. Values in here
aren't the values written to the register to have the default to be always on. */