diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2022-08-03 22:18:18 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-08-18 14:51:00 +0000 |
| commit | 665476df2bf16c84ccf7037bde67d76cc0604673 (patch) | |
| tree | 2abf2341629a79d9aff5f6da224ccd736febbdf5 /src/soc/amd/mendocino/chip.h | |
| parent | 1a8eb6c02103727431ac1ea23f4f507e49f3cde7 (diff) | |
soc/amd/mendocino: enable CPPC feature
This is sort-of reverts commit cbf290c692b2 ("soc/amd/sabrina: drop
CPPC code"), since it turned out that the CPPC feature is supported
on Sabrina (now Mendocino) despite this being missing from the
documentation I looked at when writing the patch referenced above.
Since the CPPC ACPI code generation functionality has been moved to
common code, this isn't a direct revert.
BUG=b:237336330
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1c059653eeae207d723c77e8a78b19c86e362296
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/soc/amd/mendocino/chip.h')
| -rw-r--r-- | src/soc/amd/mendocino/chip.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h index 97de7e9fe9..2122262147 100644 --- a/src/soc/amd/mendocino/chip.h +++ b/src/soc/amd/mendocino/chip.h @@ -69,6 +69,13 @@ struct soc_amd_mendocino_config { uint8_t system_configuration; + uint8_t cppc_ctrl; + uint8_t cppc_perf_limit_max_range; + uint8_t cppc_perf_limit_min_range; + uint8_t cppc_epp_max_range; + uint8_t cppc_epp_min_range; + uint8_t cppc_preferred_cores; + /* telemetry settings */ uint32_t telemetry_vddcrvddfull_scale_current_mA; uint32_t telemetry_vddcrvddoffset; |