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author | Anand Vaikar <a.vaikar2021@gmail.com> | 2024-06-17 10:46:17 +0530 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2024-06-18 13:08:00 +0000 |
commit | 6e8d0122ebac6d641304c522c5f467723a1e2468 (patch) | |
tree | 7a68bbf32ee17472dbd6133af4e960efe70237f7 /src/soc/amd/mendocino/acpi.c | |
parent | 3d523c4cd84bcf85b4908e8df7ce2b26332be88f (diff) |
soc/amd/cezanne: Add AMD Renoir SOC support
Add AMD SOC Family 17h Renoir CPUIDs per PPR doc #55922
Renoir is similar to Cezanne with only differences in CCX count.
Cezanne has one Zen3 CCX with 8 cores per CCX compared to
the two Zen2 CCX with 4 cores per CCX. Hence, coreboot side
Cezanne SOC code should be mostly compatible with Renoir and
can be leveraged.
Change-Id: I6b43eb782527351c79b835d094a5b61103cd6642
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83099
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/mendocino/acpi.c')
0 files changed, 0 insertions, 0 deletions