diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2022-08-03 22:18:18 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-08-18 14:51:00 +0000 |
| commit | 665476df2bf16c84ccf7037bde67d76cc0604673 (patch) | |
| tree | 2abf2341629a79d9aff5f6da224ccd736febbdf5 /src/soc/amd/mendocino/acpi.c | |
| parent | 1a8eb6c02103727431ac1ea23f4f507e49f3cde7 (diff) | |
soc/amd/mendocino: enable CPPC feature
This is sort-of reverts commit cbf290c692b2 ("soc/amd/sabrina: drop
CPPC code"), since it turned out that the CPPC feature is supported
on Sabrina (now Mendocino) despite this being missing from the
documentation I looked at when writing the patch referenced above.
Since the CPPC ACPI code generation functionality has been moved to
common code, this isn't a direct revert.
BUG=b:237336330
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1c059653eeae207d723c77e8a78b19c86e362296
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/soc/amd/mendocino/acpi.c')
| -rw-r--r-- | src/soc/amd/mendocino/acpi.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index 334063aa5b..75dcf82efc 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -7,6 +7,7 @@ #include <acpi/acpi.h> #include <acpi/acpigen.h> #include <amdblocks/acpi.h> +#include <amdblocks/cppc.h> #include <amdblocks/cpu.h> #include <amdblocks/acpimmio.h> #include <amdblocks/ioapic.h> @@ -358,6 +359,8 @@ void generate_cpu_entries(const struct device *device) acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core, CSD_HW_ALL, 0); + generate_cppc_entries(cpu); + acpigen_pop_len(); } |