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authorFelix Held <felix-coreboot@felixheld.de>2022-09-12 16:18:45 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-09-14 18:04:49 +0000
commit40a38cc8f0c30aef4675fbf3096cb3a9b225fc11 (patch)
treed3e7466b6d0070bfb584fc26442df9a6e1ec7de6 /src/soc/amd/mendocino/Kconfig
parentc3e36ea20b08abcd383d8788484e9f978d0569f2 (diff)
soc/amd/mendocino: Add support for separate RW A/B partition SPL file
Add support for having different Security Patch Level (SPL) table files in the read-only and the read-write A/B partitions. This allows the SPL table file in the main or RO FMAP partition to only cover the embedded firmware binaries in that partition and have a separate SPL file in the RW A and B partitions that covers the embedded firmware binaries in the RW partitions. BUG=b:243470283 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1ba8c370ce14f7ec88e7ef2f9d0b64d6bb4fa176 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/mendocino/Kconfig')
-rw-r--r--src/soc/amd/mendocino/Kconfig15
1 files changed, 15 insertions, 0 deletions
diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig
index 7155aaba0a..d7c5372ee8 100644
--- a/src/soc/amd/mendocino/Kconfig
+++ b/src/soc/amd/mendocino/Kconfig
@@ -421,6 +421,21 @@ config SPL_TABLE_FILE
depends on HAVE_SPL_FILE
default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/TypeId0x55_SplTableBl_MDN.sbin"
+config HAVE_SPL_RW_AB_FILE
+ bool "Have a separate mainboard-specific SPL file in RW A/B partitions"
+ default n
+ depends on HAVE_SPL_FILE
+ depends on VBOOT_SLOTS_RW_AB
+ help
+ Have separate mainboard-specific Security Patch Level (SPL) table
+ file for the RW A/B FMAP partitions. See the help text of
+ HAVE_SPL_FILE for a more detailed description.
+
+config SPL_RW_AB_TABLE_FILE
+ string "Separate SPL table file for RW A/B partitions"
+ depends on HAVE_SPL_RW_AB_FILE
+ default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/TypeId0x55_SplTableBl_MDN.sbin"
+
config PSP_SOFTFUSE_BITS
string "PSP Soft Fuse bits to enable"
default "34 28 6"