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author | Felix Held <felix-coreboot@felixheld.de> | 2023-03-24 19:26:49 +0100 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-29 16:16:43 +0000 |
commit | 4057ab4f314ae17402fa7635d17d86304b9ce060 (patch) | |
tree | 0f9a500e147d4685dd4d4660954f61216d07d2e7 /src/soc/amd/mendocino/Kconfig | |
parent | ad52185c2dab095cbf65f3d55976f47363d5672e (diff) |
soc/amd/common/block/cpu/tsc/tsc_freq: use get_pstate_core_freq
Use get_pstate_core_freq instead of open-coding the calculations in
tsc_freq_mhz. In the case of the CPU frequency divider being 0,
get_pstate_core_freq will return 0; in this case that shouldn't happen,
TSC_DEFAULT_FREQ_MHZ will be used as frequency, since for the TSC
frequency it's better to err on the end of the expected frequency being
too high which will cause longer than expected delays instead of too
short delays.
Now that the code is using get_pstate_core_freq, this code is valid for
Glinda too, so also remove the comment on the
SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H option being selected in the Glinda
Kconfig. This Kconfig option will be renamed in a follow-up patch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I01168834d4018c92f44782eda0c65b1aa392030d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/mendocino/Kconfig')
0 files changed, 0 insertions, 0 deletions