diff options
| author | Robert Zieba <robertzieba@google.com> | 2022-10-03 14:50:55 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-10-26 22:02:32 +0000 |
| commit | b3b27f7dea3ac7170adfbfc7e6d4ca7bde9ab780 (patch) | |
| tree | 0e1c20fd075b638563f4569ca984a048c34c08b6 /src/soc/amd/mendocino/Kconfig | |
| parent | 956432cbb7f0a5a1618fb1111158cf3a8ede5f60 (diff) | |
soc/amd/mendocino: Enable GPP clk req disabling for disabled devices
Enable GPP clk req disabling for disabled PCIe devices. If a clk req
line is enabled for a PCIe device that is not actually present and
enabled then the L1SS could get confused and cause issues with
suspending the SoC.
BUG=b:250009974
TEST=Ran on skyrim proto device, verified that clk reqs are set
appropriately
Change-Id: I6c840f2fa3f9358f58c0386134d23511ff880248
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68139
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/mendocino/Kconfig')
| -rw-r--r-- | src/soc/amd/mendocino/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index d31b29dd43..9caee1eb5e 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -75,6 +75,7 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_PCI # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PCI_MMCONF select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ select SOC_AMD_COMMON_BLOCK_PM # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PSP_GEN2 # TODO: Check if this is still correct |