diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-03-23 01:28:28 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-24 13:56:24 +0000 |
| commit | 6ba67ab2db8f7e95c9a28beeea2061b55e5b64d1 (patch) | |
| tree | a50fd46e0221869223b768f86a24884f17c8a176 /src/soc/amd/glinda | |
| parent | 5630506fc9810735a1ffca7e7b1cd533c5d689d5 (diff) | |
soc/amd/*/include/msr: drop _LO part from PSTATE definition names
The _LO part in the definition names is a leftover from before moving to
the pstate_msr union access to the bitfield elements where it still
mattered if a bit was in the lower of higher half of the MSR. With the
mask-and-shift access to the two parts of the MSR being gone, the _LO
part in the name isn't useful any more and possibly a bit misleading, so
drop that part.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib43c71e946388c944ecf40659d4c12ca02a27a5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73927
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/glinda')
| -rw-r--r-- | src/soc/amd/glinda/acpi.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/glinda/include/soc/msr.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index ce0c7e6001..1accc962d4 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -106,7 +106,7 @@ uint32_t get_pstate_core_freq(union pstate_msr pstate_reg) core_freq_mul = pstate_reg.cpu_fid_0_11; /* CPU frequency is 5 * core_freq_mul */ - return PSTATE_DEF_LO_CORE_FREQ_BASE * core_freq_mul; + return PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul; } uint32_t get_pstate_core_power(union pstate_msr pstate_reg) diff --git a/src/soc/amd/glinda/include/soc/msr.h b/src/soc/amd/glinda/include/soc/msr.h index 2c5b933b96..3f9254971c 100644 --- a/src/soc/amd/glinda/include/soc/msr.h +++ b/src/soc/amd/glinda/include/soc/msr.h @@ -20,7 +20,7 @@ union pstate_msr { uint64_t raw; }; -#define PSTATE_DEF_LO_CORE_FREQ_BASE 5 +#define PSTATE_DEF_CORE_FREQ_BASE 5 /* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */ #define SERIAL_VID_DECODE_MICROVOLTS 5000 |