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authorFelix Held <felix-coreboot@felixheld.de>2023-02-27 23:56:39 +0100
committerFelix Held <felix-coreboot@felixheld.de>2023-02-28 23:45:04 +0000
commit0a466040e0dc3351ac819ba00146f284e5f70f05 (patch)
treeac3ce1a7d8f14775d323acd05999d417f56d53ff /src/soc/amd/glinda
parent54c80e1df16d356dc73030903daece5fcb50e7bc (diff)
soc/amd: introduce and use PSTATE_MSR macro
Instead of adding the P-state number to the PSTATE_0_MSR number to get the P-state MSR number for the rdmsr call, provide a macro that directly calculates the MSR number for a given power state. Also drop the unused PSTATE_[1..4]_MSR definitions which also didn't cover all P-state MSRs available in the hardware. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If85acf556efe82c209e1608e56c05f7a2a748403 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc/amd/glinda')
-rw-r--r--src/soc/amd/glinda/acpi.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c
index 31723b1b4f..675ab20f12 100644
--- a/src/soc/amd/glinda/acpi.c
+++ b/src/soc/amd/glinda/acpi.c
@@ -203,7 +203,7 @@ static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT;
for (pstate = 0; pstate <= max_pstate; pstate++) {
- pstate_def = rdmsr(PSTATE_0_MSR + pstate);
+ pstate_def = rdmsr(PSTATE_MSR(pstate));
pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK)
>> PSTATE_DEF_HI_ENABLE_SHIFT;