diff options
author | Felix Held <felix-coreboot@felixheld.de> | 2023-03-24 16:30:55 +0100 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-29 16:15:10 +0000 |
commit | a63f859553a29842fd8d65ae8a6523cd429a5f85 (patch) | |
tree | ccf769584dc8e02611be5123f2721f41a21023f3 /src/soc/amd/glinda | |
parent | c08d804f01d88ac028c7271f0efed07373c3bc97 (diff) |
soc/amd/common/cpu/tsc: factor out family-specific get_pstate_core_freq
Factor out the get_pstate_core_freq function from the SoC's acpi.c files
to both avoid duplication and to also be able to use the same function
in the TSC frequency calculation in a follow-up patch. The family 17h
and 19h SoCs use the same frequency encoding in the P state MSRs while
the family 1Ah SoCs use a different encoding. The family 15h and 16h
SoCs use another encoding, but since this isn't implemented in
Stoneyridge's acpi.c, this will be added in a follow-up patch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8619822c2c61e06ae5db86896d5323c9b105b25b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/glinda')
-rw-r--r-- | src/soc/amd/glinda/Kconfig | 1 | ||||
-rw-r--r-- | src/soc/amd/glinda/acpi.c | 13 | ||||
-rw-r--r-- | src/soc/amd/glinda/include/soc/msr.h | 2 |
3 files changed, 1 insertions, 15 deletions
diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index 5e9b7f95bb..c68ee47b00 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -44,6 +44,7 @@ config SOC_AMD_GLINDA select SOC_AMD_COMMON_BLOCK_APOB # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_APOB_HASH # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH select SOC_AMD_COMMON_BLOCK_DATA_FABRIC select SOC_AMD_COMMON_BLOCK_EMMC # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES # TODO: Check if this is still correct diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index 850bc6c5af..49fb658d63 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -16,11 +16,9 @@ #include <arch/smp/mpspec.h> #include <console/console.h> #include <cpu/amd/cpuid.h> -#include <cpu/amd/msr.h> #include <cpu/x86/smm.h> #include <soc/acpi.h> #include <soc/iomap.h> -#include <soc/msr.h> #include <types.h> #include "chip.h" @@ -98,17 +96,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->flags |= cfg->common_config.fadt_flags; /* additional board-specific flags */ } -uint32_t get_pstate_core_freq(union pstate_msr pstate_reg) -{ - uint32_t core_freq_mul; - - /* Core frequency multiplier */ - core_freq_mul = pstate_reg.cpu_fid_0_11; - - /* CPU frequency is 5 * core_freq_mul */ - return PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul; -} - const acpi_cstate_t cstate_cfg_table[] = { [0] = { .ctype = 1, diff --git a/src/soc/amd/glinda/include/soc/msr.h b/src/soc/amd/glinda/include/soc/msr.h index ad4d9d0445..2f40d395f3 100644 --- a/src/soc/amd/glinda/include/soc/msr.h +++ b/src/soc/amd/glinda/include/soc/msr.h @@ -20,8 +20,6 @@ union pstate_msr { uint64_t raw; }; -#define PSTATE_DEF_CORE_FREQ_BASE 5 - #define MSR_CPPC_CAPABILITY_1 0xc00102b0 #define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 #define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 |