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authorFelix Held <felix-coreboot@felixheld.de>2024-01-18 21:10:59 +0100
committerFelix Held <felix-coreboot@felixheld.de>2024-01-20 01:27:04 +0000
commit5b94f9a663b08ff73466c0ee97594367729ae919 (patch)
tree277c8011c404ced11ae969098536f780f747d4d5 /src/soc/amd/glinda
parent931840fbcbe9bbe9cd98a4fbc26bfa45433a13c2 (diff)
soc/amd/*/romstage: factor out FSP-M call
Move the call into the FSP code to a file in the common AMD FSP code to isolate the FSP-specific parts of the code and a preparation to make the romstage of all non-CAR AMD SoCs common. Without isolating the call into the FSP-M code, building the common romstage would fail for genoa_poc due to fsp/api.h not being in the include path. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I30cf1bee2ec1a507dc8e61eaf44067663e2505ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/80002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/glinda')
-rw-r--r--src/soc/amd/glinda/romstage.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/src/soc/amd/glinda/romstage.c b/src/soc/amd/glinda/romstage.c
index 63a6b07dc6..6b84728ad1 100644
--- a/src/soc/amd/glinda/romstage.c
+++ b/src/soc/amd/glinda/romstage.c
@@ -1,13 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <acpi/acpi.h>
#include <amdblocks/acpimmio.h>
+#include <amdblocks/fsp.h>
#include <amdblocks/memmap.h>
#include <amdblocks/pmlib.h>
#include <amdblocks/post_codes.h>
#include <console/console.h>
#include <cpu/cpu.h>
-#include <fsp/api.h>
#include <program_loading.h>
#include <romstage_common.h>
@@ -18,7 +17,7 @@ void __noreturn romstage_main(void)
/* Snapshot chipset state prior to any FSP call */
fill_chipset_state();
- fsp_memory_init(acpi_is_wakeup_s3());
+ amd_fsp_early_init();
/* Fixup settings FSP-M should not be changing */
fch_disable_legacy_dma_io();