diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-01-19 23:06:54 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-01-20 22:23:50 +0000 |
| commit | 0e9dbf084315f9cb1a5e1a7f15ed3125e38a1806 (patch) | |
| tree | 24e7f008119b06daf9423f5c36baf4ef3d6fbd16 /src/soc/amd/glinda | |
| parent | b85fd1e84f45b003baae2f0f4851a06fbe662162 (diff) | |
soc/amd/glinda,mendocino,phoenix/espi_util: add comment about register
Even though the register name begins with ESPI, it resides in the SPI
registers and not in the eSPI registers, so add a comment to point this
out to hopefully avoid some confusion.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9f8d15ceb98f51aad0816021f98ec5c78953e7f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/glinda')
| -rw-r--r-- | src/soc/amd/glinda/espi_util.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/glinda/espi_util.c b/src/soc/amd/glinda/espi_util.c index d26a29f650..067a722e41 100644 --- a/src/soc/amd/glinda/espi_util.c +++ b/src/soc/amd/glinda/espi_util.c @@ -4,7 +4,7 @@ #include <soc/espi.h> #include <types.h> -#define ESPI_CNTRL_REGISTER 0x10 +#define ESPI_CNTRL_REGISTER 0x10 /* SPI register, not eSPI register! */ #define LOCK_SPIX10_BIT2 BIT(3) #define ESPI_MUX_SPI1 BIT(2) #define ROM_ADDR_WR_PROT BIT(1) |