diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2024-01-25 19:43:35 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-01-26 19:02:58 +0000 |
| commit | 054b84294ef5e66c9ade39bccb14f6627bed24c2 (patch) | |
| tree | af8b3411cbcd886921d5a4eb09491511591545aa /src/soc/amd/glinda | |
| parent | 4687325448c7e283ebb54ca967274590587f6d26 (diff) | |
vc/amd: move verstage on PSP files to new psp_verstage folder
Move the verstage on PSP files in vendorcode from the fsp subdirectory
to a new psp_verstage subdirectory, since those files aren't specific to
the case of the FSP being used for the silicon initialization.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic47f8b18bc515600add7838f4c7afcb4fff7c004
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80209
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/glinda')
| -rw-r--r-- | src/soc/amd/glinda/psp_verstage/Makefile.mk | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/amd/glinda/psp_verstage/Makefile.mk b/src/soc/amd/glinda/psp_verstage/Makefile.mk index 472ca2d3d2..f8ad7366c5 100644 --- a/src/soc/amd/glinda/psp_verstage/Makefile.mk +++ b/src/soc/amd/glinda/psp_verstage/Makefile.mk @@ -6,14 +6,14 @@ subdirs-y += ../../common/psp_verstage verstage-generic-ccopts += -I$(src)/soc/amd/glinda/psp_verstage/include verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include -verstage-generic-ccopts += -Isrc/vendorcode/amd/fsp/glinda/include -verstage-generic-ccopts += -Isrc/vendorcode/amd/fsp/common/include +verstage-generic-ccopts += -Isrc/vendorcode/amd/psp_verstage/glinda/include +verstage-generic-ccopts += -Isrc/vendorcode/amd/psp_verstage/common/include verstage-y += svc.c verstage-y += chipset.c verstage-y += uart.c -verstage-y +=$(top)/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_startup.S -verstage-y += $(top)/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_end.S +verstage-y +=$(top)/src/vendorcode/amd/psp_verstage/common/bl_uapp/bl_uapp_startup.S +verstage-y += $(top)/src/vendorcode/amd/psp_verstage/common/bl_uapp/bl_uapp_end.S endif |