soc/amd: Add framework for Glinda SoC

This adds the initial framework for the Glinda SoC, based on what's been
done for Morgana already.

I believe that there's more that can be made common, but that work will
continue as both platforms are developed.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I43d0fdb711c441dc410a14f6bb04b808abefe920
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>

1 files changed, 67 insertions, 0 deletions

diff --git a/src/soc/amd/glinda/xhci.c b/src/soc/amd/glinda/xhci.c
new file mode 100644
index 0000000000..78ca94ff4d
--- /dev/null
+++ b/src/soc/amd/glinda/xhci.c
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* TODO: Update for Glinda */
+
+#include <amdblocks/gpio.h>
+#include <amdblocks/smi.h>
+#include <bootstate.h>
+#include <device/device.h>
+#include <device/pci_ids.h>
+#include <drivers/usb/pci_xhci/pci_xhci.h>
+#include <soc/pci_devs.h>
+#include <soc/smi.h>
+
+static const struct sci_source xhci_sci_sources[] = {
+	{
+		.scimap = SMITYPE_XHC0_PME,
+		.gpe = GEVENT_31,
+		.direction = SMI_SCI_LVL_HIGH,
+		.level = SMI_SCI_EDG
+	},
+	{
+		.scimap = SMITYPE_XHC1_PME,
+		.gpe = GEVENT_31,
+		.direction = SMI_SCI_LVL_HIGH,
+		.level = SMI_SCI_EDG
+	},
+	{
+		.scimap = SMITYPE_XHC2_PME,
+		.gpe = GEVENT_31,
+		.direction = SMI_SCI_LVL_HIGH,
+		.level = SMI_SCI_EDG
+	}
+};
+
+enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe)
+{
+	if (dev->bus->dev->path.type != DEVICE_PATH_PCI)
+		return CB_ERR_ARG;
+
+	if (dev->path.type != DEVICE_PATH_PCI)
+		return CB_ERR_ARG;
+
+	if (dev->bus->dev->path.pci.devfn == PCIE_ABC_A_DEVFN) {
+		if (dev->path.pci.devfn == XHCI0_DEVFN) {
+			*gpe = xhci_sci_sources[0].gpe;
+			return CB_SUCCESS;
+		} else if (dev->path.pci.devfn == XHCI1_DEVFN) {
+			*gpe = xhci_sci_sources[1].gpe;
+			return CB_SUCCESS;
+		}
+	} else if (dev->bus->dev->path.pci.devfn == PCIE_GPP_C_DEVFN) {
+		if (dev->path.pci.devfn == XHCI2_DEVFN
+		    && dev->device == PCI_DID_AMD_FAM17H_MODELA0H_XHCI2) {
+			*gpe = xhci_sci_sources[2].gpe;
+			return CB_SUCCESS;
+		}
+	}
+
+	return CB_ERR_ARG;
+}
+
+static void configure_xhci_sci(void *unused)
+{
+	gpe_configure_sci(xhci_sci_sources, ARRAY_SIZE(xhci_sci_sources) - 1);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, configure_xhci_sci, NULL);