diff options
| author | Maximilian Brune <maximilian.brune@9elements.com> | 2024-07-30 12:46:18 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-09-30 16:22:20 +0000 |
| commit | 540d605f484913b885af9fd2b3084db685770960 (patch) | |
| tree | f268409618a8181d48f27debc7e3facf5b5883f1 /src/soc/amd/glinda/include | |
| parent | aed7a871b2520eff698dde22ffdae37f971bd92c (diff) | |
soc/amd/glinda: Update pci int defs
Update IRQs according to datasheet/PPR.
source:
PPR #57254 Rev 1.59 Table 137
Change-Id: I843e5e2b01301eb02cb5be347e122cffbe76d80d
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84375
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/glinda/include')
| -rw-r--r-- | src/soc/amd/glinda/include/soc/amd_pci_int_defs.h | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h b/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h index ebe1d2ceae..3a9d9b5f44 100644 --- a/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h +++ b/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h @@ -32,20 +32,16 @@ #define PIRQ_ASF 0x12 /* ASF */ /* 0x13-0x15 reserved */ #define PIRQ_PMON 0x16 /* Performance Monitor */ -#define PIRQ_SD 0x17 /* SD */ -/* 0x18-0x19 reserved */ +/* 0x17-0x19 reserved */ #define PIRQ_SDIO 0x1a /* SDIO */ /* 0x1b-0x1f reserved */ #define PIRQ_CIR 0x20 /* CIR, no IRQ connected */ #define PIRQ_GPIOA 0x21 /* GPIOa from PAD_FANIN0 */ #define PIRQ_GPIOB 0x22 /* GPIOb from PAD_FANOUT0 */ #define PIRQ_GPIOC 0x23 /* GPIOc no IRQ connected */ -/* 0x24-0x4f reserved */ -#define PIRQ_GPP0 0x50 /* GPPInt0 */ -#define PIRQ_GPP1 0x51 /* GPPInt1 */ -#define PIRQ_GPP2 0x52 /* GPPInt2 */ -#define PIRQ_GPP3 0x53 /* GPPInt3 */ -/* 0x54-0x61 reserved */ +/* 0x24-0x5f reserved */ +#define PIRQ_GSCI 0x60 /* GEventSci Interrupt */ +#define PIRQ_GSMI 0x61 /* GEventSmi Interrupt */ #define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ /* 0x63-0x6f reserved */ #define PIRQ_I2C0 0x70 /* I2C0 */ |