diff options
author | Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> | 2023-09-21 23:33:34 +0530 |
---|---|---|
committer | Subrata Banik <subratabanik@google.com> | 2023-10-04 05:47:54 +0000 |
commit | 4f062ec34b6e344e88ceaf7460675a860f10a2b6 (patch) | |
tree | 8d294bd042028d1173d356961b0f445f7f993082 /src/soc/amd/glinda/cpu.c | |
parent | c0dfd982baa461b055cdb52b7ac56e7b337795f5 (diff) |
soc/intel/cse: Add function to get cse_bp_info early
PSR data is created and stored in CSE data partition. In platforms that
employ CSE Lite SKU firmware, a firmware downgrade involves clearing of
CSE data partition which results in PSR data being lost. The PSR data
needs to be preserved across the firmware downgrade flow. CSE Lite SKU
firmware supports command to backup PSR data, and this command can be
sent only in post-RAM stages. So the cse_fw_sync actions needs to be
moved to ramstage.
Sending cse_get_bp_info command in ramstage takes additional boot time
of ~45-55ms on rex. To avoid the boot time penalty, this patch provides
an API to get the cse_bp_info in early romstage. The response data is
then migrated to cbmem once memory is initialized. The same data in
cbmem can be utilized in ramstage to perform other cse_fw_sync actions.
This patch also adds check to validate cse_bp_info in cbmem and avoids
sending the command again if the data is valid.
BUG=b:273207144
TEST=Verify the command works in early romstage, data is migrated to
cbmem and valid data is available in ramstage on rex.
Change-Id: Ib1e72c950ba0f4911924805f501ec1bd54b6ba3c
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78053
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/glinda/cpu.c')
0 files changed, 0 insertions, 0 deletions