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| author | Chris Wang <chris.wang@amd.corp-partner.google.com> | 2023-02-20 10:27:50 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-04 02:28:45 +0000 |
| commit | 50aa3d99215b558f959fceed891ed04db648739e (patch) | |
| tree | c904632687ea8be392c2ee059789e5561902916f /src/soc/amd/glinda/chipset.cb | |
| parent | 12bfe6bc95494f2a993c4222812d8960a66282ba (diff) | |
soc/amd/mendocino: Remove the SPL DPTC parameter
The SPL parameter for DPTC settings is not available for STT-enabled
platforms. It needs to be removed to avoid confusing STT calculations.
BUG=b:265267957
BRANCH=none
TEST=Run the WebGL aquarium with 5000 fish and verify that
there are no power drop peaks.
Change-Id: I8e6dad7d24883f8aadce83ebac401ecd4137d61a
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Diffstat (limited to 'src/soc/amd/glinda/chipset.cb')
0 files changed, 0 insertions, 0 deletions